ppc405_uc.c (42974B)
1/* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "qemu/osdep.h" 26#include "qemu/units.h" 27#include "qapi/error.h" 28#include "cpu.h" 29#include "hw/ppc/ppc.h" 30#include "hw/i2c/ppc4xx_i2c.h" 31#include "hw/irq.h" 32#include "ppc405.h" 33#include "hw/char/serial.h" 34#include "qemu/timer.h" 35#include "sysemu/reset.h" 36#include "sysemu/sysemu.h" 37#include "exec/address-spaces.h" 38#include "hw/intc/ppc-uic.h" 39#include "hw/qdev-properties.h" 40#include "qapi/error.h" 41 42//#define DEBUG_OPBA 43//#define DEBUG_SDRAM 44//#define DEBUG_GPIO 45//#define DEBUG_SERIAL 46//#define DEBUG_OCM 47//#define DEBUG_GPT 48//#define DEBUG_CLOCKS 49//#define DEBUG_CLOCKS_LL 50 51ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, 52 uint32_t flags) 53{ 54 CPUState *cs = env_cpu(env); 55 ram_addr_t bdloc; 56 int i, n; 57 58 /* We put the bd structure at the top of memory */ 59 if (bd->bi_memsize >= 0x01000000UL) 60 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 61 else 62 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 63 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 64 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 65 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 66 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 67 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 68 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 69 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 70 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 71 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 72 for (i = 0; i < 6; i++) { 73 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 74 } 75 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 76 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 77 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 78 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 79 for (i = 0; i < 4; i++) { 80 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 81 } 82 for (i = 0; i < 32; i++) { 83 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 84 } 85 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 86 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 87 for (i = 0; i < 6; i++) { 88 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 89 } 90 n = 0x6A; 91 if (flags & 0x00000001) { 92 for (i = 0; i < 6; i++) 93 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 94 } 95 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 96 n += 4; 97 for (i = 0; i < 2; i++) { 98 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 99 n += 4; 100 } 101 102 return bdloc; 103} 104 105/*****************************************************************************/ 106/* Shared peripherals */ 107 108/*****************************************************************************/ 109/* Peripheral local bus arbitrer */ 110enum { 111 PLB3A0_ACR = 0x077, 112 PLB4A0_ACR = 0x081, 113 PLB0_BESR = 0x084, 114 PLB0_BEAR = 0x086, 115 PLB0_ACR = 0x087, 116 PLB4A1_ACR = 0x089, 117}; 118 119typedef struct ppc4xx_plb_t ppc4xx_plb_t; 120struct ppc4xx_plb_t { 121 uint32_t acr; 122 uint32_t bear; 123 uint32_t besr; 124}; 125 126static uint32_t dcr_read_plb (void *opaque, int dcrn) 127{ 128 ppc4xx_plb_t *plb; 129 uint32_t ret; 130 131 plb = opaque; 132 switch (dcrn) { 133 case PLB0_ACR: 134 ret = plb->acr; 135 break; 136 case PLB0_BEAR: 137 ret = plb->bear; 138 break; 139 case PLB0_BESR: 140 ret = plb->besr; 141 break; 142 default: 143 /* Avoid gcc warning */ 144 ret = 0; 145 break; 146 } 147 148 return ret; 149} 150 151static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 152{ 153 ppc4xx_plb_t *plb; 154 155 plb = opaque; 156 switch (dcrn) { 157 case PLB0_ACR: 158 /* We don't care about the actual parameters written as 159 * we don't manage any priorities on the bus 160 */ 161 plb->acr = val & 0xF8000000; 162 break; 163 case PLB0_BEAR: 164 /* Read only */ 165 break; 166 case PLB0_BESR: 167 /* Write-clear */ 168 plb->besr &= ~val; 169 break; 170 } 171} 172 173static void ppc4xx_plb_reset (void *opaque) 174{ 175 ppc4xx_plb_t *plb; 176 177 plb = opaque; 178 plb->acr = 0x00000000; 179 plb->bear = 0x00000000; 180 plb->besr = 0x00000000; 181} 182 183void ppc4xx_plb_init(CPUPPCState *env) 184{ 185 ppc4xx_plb_t *plb; 186 187 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 188 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 189 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 190 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 191 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 192 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 193 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 194 qemu_register_reset(ppc4xx_plb_reset, plb); 195} 196 197/*****************************************************************************/ 198/* PLB to OPB bridge */ 199enum { 200 POB0_BESR0 = 0x0A0, 201 POB0_BESR1 = 0x0A2, 202 POB0_BEAR = 0x0A4, 203}; 204 205typedef struct ppc4xx_pob_t ppc4xx_pob_t; 206struct ppc4xx_pob_t { 207 uint32_t bear; 208 uint32_t besr0; 209 uint32_t besr1; 210}; 211 212static uint32_t dcr_read_pob (void *opaque, int dcrn) 213{ 214 ppc4xx_pob_t *pob; 215 uint32_t ret; 216 217 pob = opaque; 218 switch (dcrn) { 219 case POB0_BEAR: 220 ret = pob->bear; 221 break; 222 case POB0_BESR0: 223 ret = pob->besr0; 224 break; 225 case POB0_BESR1: 226 ret = pob->besr1; 227 break; 228 default: 229 /* Avoid gcc warning */ 230 ret = 0; 231 break; 232 } 233 234 return ret; 235} 236 237static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 238{ 239 ppc4xx_pob_t *pob; 240 241 pob = opaque; 242 switch (dcrn) { 243 case POB0_BEAR: 244 /* Read only */ 245 break; 246 case POB0_BESR0: 247 /* Write-clear */ 248 pob->besr0 &= ~val; 249 break; 250 case POB0_BESR1: 251 /* Write-clear */ 252 pob->besr1 &= ~val; 253 break; 254 } 255} 256 257static void ppc4xx_pob_reset (void *opaque) 258{ 259 ppc4xx_pob_t *pob; 260 261 pob = opaque; 262 /* No error */ 263 pob->bear = 0x00000000; 264 pob->besr0 = 0x0000000; 265 pob->besr1 = 0x0000000; 266} 267 268static void ppc4xx_pob_init(CPUPPCState *env) 269{ 270 ppc4xx_pob_t *pob; 271 272 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 273 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 274 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 275 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 276 qemu_register_reset(ppc4xx_pob_reset, pob); 277} 278 279/*****************************************************************************/ 280/* OPB arbitrer */ 281typedef struct ppc4xx_opba_t ppc4xx_opba_t; 282struct ppc4xx_opba_t { 283 MemoryRegion io; 284 uint8_t cr; 285 uint8_t pr; 286}; 287 288static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 289{ 290 ppc4xx_opba_t *opba; 291 uint32_t ret; 292 293#ifdef DEBUG_OPBA 294 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 295#endif 296 opba = opaque; 297 switch (addr) { 298 case 0x00: 299 ret = opba->cr; 300 break; 301 case 0x01: 302 ret = opba->pr; 303 break; 304 default: 305 ret = 0x00; 306 break; 307 } 308 309 return ret; 310} 311 312static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 313 unsigned size) 314{ 315 ppc4xx_opba_t *opba; 316 317#ifdef DEBUG_OPBA 318 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 319 value); 320#endif 321 opba = opaque; 322 switch (addr) { 323 case 0x00: 324 opba->cr = value & 0xF8; 325 break; 326 case 0x01: 327 opba->pr = value & 0xFF; 328 break; 329 default: 330 break; 331 } 332} 333static const MemoryRegionOps opba_ops = { 334 .read = opba_readb, 335 .write = opba_writeb, 336 .impl.min_access_size = 1, 337 .impl.max_access_size = 1, 338 .valid.min_access_size = 1, 339 .valid.max_access_size = 4, 340 .endianness = DEVICE_BIG_ENDIAN, 341}; 342 343static void ppc4xx_opba_reset (void *opaque) 344{ 345 ppc4xx_opba_t *opba; 346 347 opba = opaque; 348 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 349 opba->pr = 0x11; 350} 351 352static void ppc4xx_opba_init(hwaddr base) 353{ 354 ppc4xx_opba_t *opba; 355 356 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 357#ifdef DEBUG_OPBA 358 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 359#endif 360 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 361 memory_region_add_subregion(get_system_memory(), base, &opba->io); 362 qemu_register_reset(ppc4xx_opba_reset, opba); 363} 364 365/*****************************************************************************/ 366/* Code decompression controller */ 367/* XXX: TODO */ 368 369/*****************************************************************************/ 370/* Peripheral controller */ 371typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 372struct ppc4xx_ebc_t { 373 uint32_t addr; 374 uint32_t bcr[8]; 375 uint32_t bap[8]; 376 uint32_t bear; 377 uint32_t besr0; 378 uint32_t besr1; 379 uint32_t cfg; 380}; 381 382enum { 383 EBC0_CFGADDR = 0x012, 384 EBC0_CFGDATA = 0x013, 385}; 386 387static uint32_t dcr_read_ebc (void *opaque, int dcrn) 388{ 389 ppc4xx_ebc_t *ebc; 390 uint32_t ret; 391 392 ebc = opaque; 393 switch (dcrn) { 394 case EBC0_CFGADDR: 395 ret = ebc->addr; 396 break; 397 case EBC0_CFGDATA: 398 switch (ebc->addr) { 399 case 0x00: /* B0CR */ 400 ret = ebc->bcr[0]; 401 break; 402 case 0x01: /* B1CR */ 403 ret = ebc->bcr[1]; 404 break; 405 case 0x02: /* B2CR */ 406 ret = ebc->bcr[2]; 407 break; 408 case 0x03: /* B3CR */ 409 ret = ebc->bcr[3]; 410 break; 411 case 0x04: /* B4CR */ 412 ret = ebc->bcr[4]; 413 break; 414 case 0x05: /* B5CR */ 415 ret = ebc->bcr[5]; 416 break; 417 case 0x06: /* B6CR */ 418 ret = ebc->bcr[6]; 419 break; 420 case 0x07: /* B7CR */ 421 ret = ebc->bcr[7]; 422 break; 423 case 0x10: /* B0AP */ 424 ret = ebc->bap[0]; 425 break; 426 case 0x11: /* B1AP */ 427 ret = ebc->bap[1]; 428 break; 429 case 0x12: /* B2AP */ 430 ret = ebc->bap[2]; 431 break; 432 case 0x13: /* B3AP */ 433 ret = ebc->bap[3]; 434 break; 435 case 0x14: /* B4AP */ 436 ret = ebc->bap[4]; 437 break; 438 case 0x15: /* B5AP */ 439 ret = ebc->bap[5]; 440 break; 441 case 0x16: /* B6AP */ 442 ret = ebc->bap[6]; 443 break; 444 case 0x17: /* B7AP */ 445 ret = ebc->bap[7]; 446 break; 447 case 0x20: /* BEAR */ 448 ret = ebc->bear; 449 break; 450 case 0x21: /* BESR0 */ 451 ret = ebc->besr0; 452 break; 453 case 0x22: /* BESR1 */ 454 ret = ebc->besr1; 455 break; 456 case 0x23: /* CFG */ 457 ret = ebc->cfg; 458 break; 459 default: 460 ret = 0x00000000; 461 break; 462 } 463 break; 464 default: 465 ret = 0x00000000; 466 break; 467 } 468 469 return ret; 470} 471 472static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 473{ 474 ppc4xx_ebc_t *ebc; 475 476 ebc = opaque; 477 switch (dcrn) { 478 case EBC0_CFGADDR: 479 ebc->addr = val; 480 break; 481 case EBC0_CFGDATA: 482 switch (ebc->addr) { 483 case 0x00: /* B0CR */ 484 break; 485 case 0x01: /* B1CR */ 486 break; 487 case 0x02: /* B2CR */ 488 break; 489 case 0x03: /* B3CR */ 490 break; 491 case 0x04: /* B4CR */ 492 break; 493 case 0x05: /* B5CR */ 494 break; 495 case 0x06: /* B6CR */ 496 break; 497 case 0x07: /* B7CR */ 498 break; 499 case 0x10: /* B0AP */ 500 break; 501 case 0x11: /* B1AP */ 502 break; 503 case 0x12: /* B2AP */ 504 break; 505 case 0x13: /* B3AP */ 506 break; 507 case 0x14: /* B4AP */ 508 break; 509 case 0x15: /* B5AP */ 510 break; 511 case 0x16: /* B6AP */ 512 break; 513 case 0x17: /* B7AP */ 514 break; 515 case 0x20: /* BEAR */ 516 break; 517 case 0x21: /* BESR0 */ 518 break; 519 case 0x22: /* BESR1 */ 520 break; 521 case 0x23: /* CFG */ 522 break; 523 default: 524 break; 525 } 526 break; 527 default: 528 break; 529 } 530} 531 532static void ebc_reset (void *opaque) 533{ 534 ppc4xx_ebc_t *ebc; 535 int i; 536 537 ebc = opaque; 538 ebc->addr = 0x00000000; 539 ebc->bap[0] = 0x7F8FFE80; 540 ebc->bcr[0] = 0xFFE28000; 541 for (i = 0; i < 8; i++) { 542 ebc->bap[i] = 0x00000000; 543 ebc->bcr[i] = 0x00000000; 544 } 545 ebc->besr0 = 0x00000000; 546 ebc->besr1 = 0x00000000; 547 ebc->cfg = 0x80400000; 548} 549 550void ppc405_ebc_init(CPUPPCState *env) 551{ 552 ppc4xx_ebc_t *ebc; 553 554 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 555 qemu_register_reset(&ebc_reset, ebc); 556 ppc_dcr_register(env, EBC0_CFGADDR, 557 ebc, &dcr_read_ebc, &dcr_write_ebc); 558 ppc_dcr_register(env, EBC0_CFGDATA, 559 ebc, &dcr_read_ebc, &dcr_write_ebc); 560} 561 562/*****************************************************************************/ 563/* DMA controller */ 564enum { 565 DMA0_CR0 = 0x100, 566 DMA0_CT0 = 0x101, 567 DMA0_DA0 = 0x102, 568 DMA0_SA0 = 0x103, 569 DMA0_SG0 = 0x104, 570 DMA0_CR1 = 0x108, 571 DMA0_CT1 = 0x109, 572 DMA0_DA1 = 0x10A, 573 DMA0_SA1 = 0x10B, 574 DMA0_SG1 = 0x10C, 575 DMA0_CR2 = 0x110, 576 DMA0_CT2 = 0x111, 577 DMA0_DA2 = 0x112, 578 DMA0_SA2 = 0x113, 579 DMA0_SG2 = 0x114, 580 DMA0_CR3 = 0x118, 581 DMA0_CT3 = 0x119, 582 DMA0_DA3 = 0x11A, 583 DMA0_SA3 = 0x11B, 584 DMA0_SG3 = 0x11C, 585 DMA0_SR = 0x120, 586 DMA0_SGC = 0x123, 587 DMA0_SLP = 0x125, 588 DMA0_POL = 0x126, 589}; 590 591typedef struct ppc405_dma_t ppc405_dma_t; 592struct ppc405_dma_t { 593 qemu_irq irqs[4]; 594 uint32_t cr[4]; 595 uint32_t ct[4]; 596 uint32_t da[4]; 597 uint32_t sa[4]; 598 uint32_t sg[4]; 599 uint32_t sr; 600 uint32_t sgc; 601 uint32_t slp; 602 uint32_t pol; 603}; 604 605static uint32_t dcr_read_dma (void *opaque, int dcrn) 606{ 607 return 0; 608} 609 610static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 611{ 612} 613 614static void ppc405_dma_reset (void *opaque) 615{ 616 ppc405_dma_t *dma; 617 int i; 618 619 dma = opaque; 620 for (i = 0; i < 4; i++) { 621 dma->cr[i] = 0x00000000; 622 dma->ct[i] = 0x00000000; 623 dma->da[i] = 0x00000000; 624 dma->sa[i] = 0x00000000; 625 dma->sg[i] = 0x00000000; 626 } 627 dma->sr = 0x00000000; 628 dma->sgc = 0x00000000; 629 dma->slp = 0x7C000000; 630 dma->pol = 0x00000000; 631} 632 633static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 634{ 635 ppc405_dma_t *dma; 636 637 dma = g_malloc0(sizeof(ppc405_dma_t)); 638 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 639 qemu_register_reset(&ppc405_dma_reset, dma); 640 ppc_dcr_register(env, DMA0_CR0, 641 dma, &dcr_read_dma, &dcr_write_dma); 642 ppc_dcr_register(env, DMA0_CT0, 643 dma, &dcr_read_dma, &dcr_write_dma); 644 ppc_dcr_register(env, DMA0_DA0, 645 dma, &dcr_read_dma, &dcr_write_dma); 646 ppc_dcr_register(env, DMA0_SA0, 647 dma, &dcr_read_dma, &dcr_write_dma); 648 ppc_dcr_register(env, DMA0_SG0, 649 dma, &dcr_read_dma, &dcr_write_dma); 650 ppc_dcr_register(env, DMA0_CR1, 651 dma, &dcr_read_dma, &dcr_write_dma); 652 ppc_dcr_register(env, DMA0_CT1, 653 dma, &dcr_read_dma, &dcr_write_dma); 654 ppc_dcr_register(env, DMA0_DA1, 655 dma, &dcr_read_dma, &dcr_write_dma); 656 ppc_dcr_register(env, DMA0_SA1, 657 dma, &dcr_read_dma, &dcr_write_dma); 658 ppc_dcr_register(env, DMA0_SG1, 659 dma, &dcr_read_dma, &dcr_write_dma); 660 ppc_dcr_register(env, DMA0_CR2, 661 dma, &dcr_read_dma, &dcr_write_dma); 662 ppc_dcr_register(env, DMA0_CT2, 663 dma, &dcr_read_dma, &dcr_write_dma); 664 ppc_dcr_register(env, DMA0_DA2, 665 dma, &dcr_read_dma, &dcr_write_dma); 666 ppc_dcr_register(env, DMA0_SA2, 667 dma, &dcr_read_dma, &dcr_write_dma); 668 ppc_dcr_register(env, DMA0_SG2, 669 dma, &dcr_read_dma, &dcr_write_dma); 670 ppc_dcr_register(env, DMA0_CR3, 671 dma, &dcr_read_dma, &dcr_write_dma); 672 ppc_dcr_register(env, DMA0_CT3, 673 dma, &dcr_read_dma, &dcr_write_dma); 674 ppc_dcr_register(env, DMA0_DA3, 675 dma, &dcr_read_dma, &dcr_write_dma); 676 ppc_dcr_register(env, DMA0_SA3, 677 dma, &dcr_read_dma, &dcr_write_dma); 678 ppc_dcr_register(env, DMA0_SG3, 679 dma, &dcr_read_dma, &dcr_write_dma); 680 ppc_dcr_register(env, DMA0_SR, 681 dma, &dcr_read_dma, &dcr_write_dma); 682 ppc_dcr_register(env, DMA0_SGC, 683 dma, &dcr_read_dma, &dcr_write_dma); 684 ppc_dcr_register(env, DMA0_SLP, 685 dma, &dcr_read_dma, &dcr_write_dma); 686 ppc_dcr_register(env, DMA0_POL, 687 dma, &dcr_read_dma, &dcr_write_dma); 688} 689 690/*****************************************************************************/ 691/* GPIO */ 692typedef struct ppc405_gpio_t ppc405_gpio_t; 693struct ppc405_gpio_t { 694 MemoryRegion io; 695 uint32_t or; 696 uint32_t tcr; 697 uint32_t osrh; 698 uint32_t osrl; 699 uint32_t tsrh; 700 uint32_t tsrl; 701 uint32_t odr; 702 uint32_t ir; 703 uint32_t rr1; 704 uint32_t isr1h; 705 uint32_t isr1l; 706}; 707 708static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 709{ 710#ifdef DEBUG_GPIO 711 printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); 712#endif 713 714 return 0; 715} 716 717static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 718 unsigned size) 719{ 720#ifdef DEBUG_GPIO 721 printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", 722 __func__, addr, size, value); 723#endif 724} 725 726static const MemoryRegionOps ppc405_gpio_ops = { 727 .read = ppc405_gpio_read, 728 .write = ppc405_gpio_write, 729 .endianness = DEVICE_NATIVE_ENDIAN, 730}; 731 732static void ppc405_gpio_reset (void *opaque) 733{ 734} 735 736static void ppc405_gpio_init(hwaddr base) 737{ 738 ppc405_gpio_t *gpio; 739 740 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 741#ifdef DEBUG_GPIO 742 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 743#endif 744 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 745 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 746 qemu_register_reset(&ppc405_gpio_reset, gpio); 747} 748 749/*****************************************************************************/ 750/* On Chip Memory */ 751enum { 752 OCM0_ISARC = 0x018, 753 OCM0_ISACNTL = 0x019, 754 OCM0_DSARC = 0x01A, 755 OCM0_DSACNTL = 0x01B, 756}; 757 758typedef struct ppc405_ocm_t ppc405_ocm_t; 759struct ppc405_ocm_t { 760 MemoryRegion ram; 761 MemoryRegion isarc_ram; 762 MemoryRegion dsarc_ram; 763 uint32_t isarc; 764 uint32_t isacntl; 765 uint32_t dsarc; 766 uint32_t dsacntl; 767}; 768 769static void ocm_update_mappings (ppc405_ocm_t *ocm, 770 uint32_t isarc, uint32_t isacntl, 771 uint32_t dsarc, uint32_t dsacntl) 772{ 773#ifdef DEBUG_OCM 774 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 775 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 776 " (%08" PRIx32 " %08" PRIx32 ")\n", 777 isarc, isacntl, dsarc, dsacntl, 778 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); 779#endif 780 if (ocm->isarc != isarc || 781 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 782 if (ocm->isacntl & 0x80000000) { 783 /* Unmap previously assigned memory region */ 784 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); 785 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 786 } 787 if (isacntl & 0x80000000) { 788 /* Map new instruction memory region */ 789#ifdef DEBUG_OCM 790 printf("OCM map ISA %08" PRIx32 "\n", isarc); 791#endif 792 memory_region_add_subregion(get_system_memory(), isarc, 793 &ocm->isarc_ram); 794 } 795 } 796 if (ocm->dsarc != dsarc || 797 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 798 if (ocm->dsacntl & 0x80000000) { 799 /* Beware not to unmap the region we just mapped */ 800 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 801 /* Unmap previously assigned memory region */ 802#ifdef DEBUG_OCM 803 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); 804#endif 805 memory_region_del_subregion(get_system_memory(), 806 &ocm->dsarc_ram); 807 } 808 } 809 if (dsacntl & 0x80000000) { 810 /* Beware not to remap the region we just mapped */ 811 if (!(isacntl & 0x80000000) || dsarc != isarc) { 812 /* Map new data memory region */ 813#ifdef DEBUG_OCM 814 printf("OCM map DSA %08" PRIx32 "\n", dsarc); 815#endif 816 memory_region_add_subregion(get_system_memory(), dsarc, 817 &ocm->dsarc_ram); 818 } 819 } 820 } 821} 822 823static uint32_t dcr_read_ocm (void *opaque, int dcrn) 824{ 825 ppc405_ocm_t *ocm; 826 uint32_t ret; 827 828 ocm = opaque; 829 switch (dcrn) { 830 case OCM0_ISARC: 831 ret = ocm->isarc; 832 break; 833 case OCM0_ISACNTL: 834 ret = ocm->isacntl; 835 break; 836 case OCM0_DSARC: 837 ret = ocm->dsarc; 838 break; 839 case OCM0_DSACNTL: 840 ret = ocm->dsacntl; 841 break; 842 default: 843 ret = 0; 844 break; 845 } 846 847 return ret; 848} 849 850static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 851{ 852 ppc405_ocm_t *ocm; 853 uint32_t isarc, dsarc, isacntl, dsacntl; 854 855 ocm = opaque; 856 isarc = ocm->isarc; 857 dsarc = ocm->dsarc; 858 isacntl = ocm->isacntl; 859 dsacntl = ocm->dsacntl; 860 switch (dcrn) { 861 case OCM0_ISARC: 862 isarc = val & 0xFC000000; 863 break; 864 case OCM0_ISACNTL: 865 isacntl = val & 0xC0000000; 866 break; 867 case OCM0_DSARC: 868 isarc = val & 0xFC000000; 869 break; 870 case OCM0_DSACNTL: 871 isacntl = val & 0xC0000000; 872 break; 873 } 874 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 875 ocm->isarc = isarc; 876 ocm->dsarc = dsarc; 877 ocm->isacntl = isacntl; 878 ocm->dsacntl = dsacntl; 879} 880 881static void ocm_reset (void *opaque) 882{ 883 ppc405_ocm_t *ocm; 884 uint32_t isarc, dsarc, isacntl, dsacntl; 885 886 ocm = opaque; 887 isarc = 0x00000000; 888 isacntl = 0x00000000; 889 dsarc = 0x00000000; 890 dsacntl = 0x00000000; 891 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 892 ocm->isarc = isarc; 893 ocm->dsarc = dsarc; 894 ocm->isacntl = isacntl; 895 ocm->dsacntl = dsacntl; 896} 897 898static void ppc405_ocm_init(CPUPPCState *env) 899{ 900 ppc405_ocm_t *ocm; 901 902 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 903 /* XXX: Size is 4096 or 0x04000000 */ 904 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, 905 &error_fatal); 906 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", 907 &ocm->isarc_ram, 0, 4 * KiB); 908 qemu_register_reset(&ocm_reset, ocm); 909 ppc_dcr_register(env, OCM0_ISARC, 910 ocm, &dcr_read_ocm, &dcr_write_ocm); 911 ppc_dcr_register(env, OCM0_ISACNTL, 912 ocm, &dcr_read_ocm, &dcr_write_ocm); 913 ppc_dcr_register(env, OCM0_DSARC, 914 ocm, &dcr_read_ocm, &dcr_write_ocm); 915 ppc_dcr_register(env, OCM0_DSACNTL, 916 ocm, &dcr_read_ocm, &dcr_write_ocm); 917} 918 919/*****************************************************************************/ 920/* General purpose timers */ 921typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 922struct ppc4xx_gpt_t { 923 MemoryRegion iomem; 924 int64_t tb_offset; 925 uint32_t tb_freq; 926 QEMUTimer *timer; 927 qemu_irq irqs[5]; 928 uint32_t oe; 929 uint32_t ol; 930 uint32_t im; 931 uint32_t is; 932 uint32_t ie; 933 uint32_t comp[5]; 934 uint32_t mask[5]; 935}; 936 937static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 938{ 939 /* XXX: TODO */ 940 return 0; 941} 942 943static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 944{ 945 /* XXX: TODO */ 946} 947 948static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 949{ 950 uint32_t mask; 951 int i; 952 953 mask = 0x80000000; 954 for (i = 0; i < 5; i++) { 955 if (gpt->oe & mask) { 956 /* Output is enabled */ 957 if (ppc4xx_gpt_compare(gpt, i)) { 958 /* Comparison is OK */ 959 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 960 } else { 961 /* Comparison is KO */ 962 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 963 } 964 } 965 mask = mask >> 1; 966 } 967} 968 969static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 970{ 971 uint32_t mask; 972 int i; 973 974 mask = 0x00008000; 975 for (i = 0; i < 5; i++) { 976 if (gpt->is & gpt->im & mask) 977 qemu_irq_raise(gpt->irqs[i]); 978 else 979 qemu_irq_lower(gpt->irqs[i]); 980 mask = mask >> 1; 981 } 982} 983 984static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 985{ 986 /* XXX: TODO */ 987} 988 989static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 990{ 991 ppc4xx_gpt_t *gpt; 992 uint32_t ret; 993 int idx; 994 995#ifdef DEBUG_GPT 996 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 997#endif 998 gpt = opaque; 999 switch (addr) { 1000 case 0x00: 1001 /* Time base counter */ 1002 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1003 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1004 break; 1005 case 0x10: 1006 /* Output enable */ 1007 ret = gpt->oe; 1008 break; 1009 case 0x14: 1010 /* Output level */ 1011 ret = gpt->ol; 1012 break; 1013 case 0x18: 1014 /* Interrupt mask */ 1015 ret = gpt->im; 1016 break; 1017 case 0x1C: 1018 case 0x20: 1019 /* Interrupt status */ 1020 ret = gpt->is; 1021 break; 1022 case 0x24: 1023 /* Interrupt enable */ 1024 ret = gpt->ie; 1025 break; 1026 case 0x80 ... 0x90: 1027 /* Compare timer */ 1028 idx = (addr - 0x80) >> 2; 1029 ret = gpt->comp[idx]; 1030 break; 1031 case 0xC0 ... 0xD0: 1032 /* Compare mask */ 1033 idx = (addr - 0xC0) >> 2; 1034 ret = gpt->mask[idx]; 1035 break; 1036 default: 1037 ret = -1; 1038 break; 1039 } 1040 1041 return ret; 1042} 1043 1044static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 1045 unsigned size) 1046{ 1047 ppc4xx_gpt_t *gpt; 1048 int idx; 1049 1050#ifdef DEBUG_I2C 1051 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1052 value); 1053#endif 1054 gpt = opaque; 1055 switch (addr) { 1056 case 0x00: 1057 /* Time base counter */ 1058 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1059 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1060 ppc4xx_gpt_compute_timer(gpt); 1061 break; 1062 case 0x10: 1063 /* Output enable */ 1064 gpt->oe = value & 0xF8000000; 1065 ppc4xx_gpt_set_outputs(gpt); 1066 break; 1067 case 0x14: 1068 /* Output level */ 1069 gpt->ol = value & 0xF8000000; 1070 ppc4xx_gpt_set_outputs(gpt); 1071 break; 1072 case 0x18: 1073 /* Interrupt mask */ 1074 gpt->im = value & 0x0000F800; 1075 break; 1076 case 0x1C: 1077 /* Interrupt status set */ 1078 gpt->is |= value & 0x0000F800; 1079 ppc4xx_gpt_set_irqs(gpt); 1080 break; 1081 case 0x20: 1082 /* Interrupt status clear */ 1083 gpt->is &= ~(value & 0x0000F800); 1084 ppc4xx_gpt_set_irqs(gpt); 1085 break; 1086 case 0x24: 1087 /* Interrupt enable */ 1088 gpt->ie = value & 0x0000F800; 1089 ppc4xx_gpt_set_irqs(gpt); 1090 break; 1091 case 0x80 ... 0x90: 1092 /* Compare timer */ 1093 idx = (addr - 0x80) >> 2; 1094 gpt->comp[idx] = value & 0xF8000000; 1095 ppc4xx_gpt_compute_timer(gpt); 1096 break; 1097 case 0xC0 ... 0xD0: 1098 /* Compare mask */ 1099 idx = (addr - 0xC0) >> 2; 1100 gpt->mask[idx] = value & 0xF8000000; 1101 ppc4xx_gpt_compute_timer(gpt); 1102 break; 1103 } 1104} 1105 1106static const MemoryRegionOps gpt_ops = { 1107 .read = ppc4xx_gpt_read, 1108 .write = ppc4xx_gpt_write, 1109 .valid.min_access_size = 4, 1110 .valid.max_access_size = 4, 1111 .endianness = DEVICE_NATIVE_ENDIAN, 1112}; 1113 1114static void ppc4xx_gpt_cb (void *opaque) 1115{ 1116 ppc4xx_gpt_t *gpt; 1117 1118 gpt = opaque; 1119 ppc4xx_gpt_set_irqs(gpt); 1120 ppc4xx_gpt_set_outputs(gpt); 1121 ppc4xx_gpt_compute_timer(gpt); 1122} 1123 1124static void ppc4xx_gpt_reset (void *opaque) 1125{ 1126 ppc4xx_gpt_t *gpt; 1127 int i; 1128 1129 gpt = opaque; 1130 timer_del(gpt->timer); 1131 gpt->oe = 0x00000000; 1132 gpt->ol = 0x00000000; 1133 gpt->im = 0x00000000; 1134 gpt->is = 0x00000000; 1135 gpt->ie = 0x00000000; 1136 for (i = 0; i < 5; i++) { 1137 gpt->comp[i] = 0x00000000; 1138 gpt->mask[i] = 0x00000000; 1139 } 1140} 1141 1142static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1143{ 1144 ppc4xx_gpt_t *gpt; 1145 int i; 1146 1147 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1148 for (i = 0; i < 5; i++) { 1149 gpt->irqs[i] = irqs[i]; 1150 } 1151 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1152#ifdef DEBUG_GPT 1153 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 1154#endif 1155 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1156 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1157 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1158} 1159 1160/*****************************************************************************/ 1161/* PowerPC 405EP */ 1162/* CPU control */ 1163enum { 1164 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1165 PPC405EP_CPC0_BOOT = 0x0F1, 1166 PPC405EP_CPC0_EPCTL = 0x0F3, 1167 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1168 PPC405EP_CPC0_UCR = 0x0F5, 1169 PPC405EP_CPC0_SRR = 0x0F6, 1170 PPC405EP_CPC0_JTAGID = 0x0F7, 1171 PPC405EP_CPC0_PCI = 0x0F9, 1172#if 0 1173 PPC405EP_CPC0_ER = xxx, 1174 PPC405EP_CPC0_FR = xxx, 1175 PPC405EP_CPC0_SR = xxx, 1176#endif 1177}; 1178 1179enum { 1180 PPC405EP_CPU_CLK = 0, 1181 PPC405EP_PLB_CLK = 1, 1182 PPC405EP_OPB_CLK = 2, 1183 PPC405EP_EBC_CLK = 3, 1184 PPC405EP_MAL_CLK = 4, 1185 PPC405EP_PCI_CLK = 5, 1186 PPC405EP_UART0_CLK = 6, 1187 PPC405EP_UART1_CLK = 7, 1188 PPC405EP_CLK_NB = 8, 1189}; 1190 1191typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1192struct ppc405ep_cpc_t { 1193 uint32_t sysclk; 1194 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1195 uint32_t boot; 1196 uint32_t epctl; 1197 uint32_t pllmr[2]; 1198 uint32_t ucr; 1199 uint32_t srr; 1200 uint32_t jtagid; 1201 uint32_t pci; 1202 /* Clock and power management */ 1203 uint32_t er; 1204 uint32_t fr; 1205 uint32_t sr; 1206}; 1207 1208static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1209{ 1210 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1211 uint32_t UART0_clk, UART1_clk; 1212 uint64_t VCO_out, PLL_out; 1213 int M, D; 1214 1215 VCO_out = 0; 1216 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1217 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1218#ifdef DEBUG_CLOCKS_LL 1219 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); 1220#endif 1221 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1222#ifdef DEBUG_CLOCKS_LL 1223 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); 1224#endif 1225 VCO_out = (uint64_t)cpc->sysclk * M * D; 1226 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1227 /* Error - unlock the PLL */ 1228 printf("VCO out of range %" PRIu64 "\n", VCO_out); 1229#if 0 1230 cpc->pllmr[1] &= ~0x80000000; 1231 goto pll_bypass; 1232#endif 1233 } 1234 PLL_out = VCO_out / D; 1235 /* Pretend the PLL is locked */ 1236 cpc->boot |= 0x00000001; 1237 } else { 1238#if 0 1239 pll_bypass: 1240#endif 1241 PLL_out = cpc->sysclk; 1242 if (cpc->pllmr[1] & 0x40000000) { 1243 /* Pretend the PLL is not locked */ 1244 cpc->boot &= ~0x00000001; 1245 } 1246 } 1247 /* Now, compute all other clocks */ 1248 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1249#ifdef DEBUG_CLOCKS_LL 1250 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); 1251#endif 1252 CPU_clk = PLL_out / D; 1253 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1254#ifdef DEBUG_CLOCKS_LL 1255 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); 1256#endif 1257 PLB_clk = CPU_clk / D; 1258 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1259#ifdef DEBUG_CLOCKS_LL 1260 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); 1261#endif 1262 OPB_clk = PLB_clk / D; 1263 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1264#ifdef DEBUG_CLOCKS_LL 1265 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); 1266#endif 1267 EBC_clk = PLB_clk / D; 1268 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1269#ifdef DEBUG_CLOCKS_LL 1270 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); 1271#endif 1272 MAL_clk = PLB_clk / D; 1273 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1274#ifdef DEBUG_CLOCKS_LL 1275 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); 1276#endif 1277 PCI_clk = PLB_clk / D; 1278 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1279#ifdef DEBUG_CLOCKS_LL 1280 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); 1281#endif 1282 UART0_clk = PLL_out / D; 1283 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1284#ifdef DEBUG_CLOCKS_LL 1285 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); 1286#endif 1287 UART1_clk = PLL_out / D; 1288#ifdef DEBUG_CLOCKS 1289 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1290 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); 1291 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1292 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1293 " UART1 %" PRIu32 "\n", 1294 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1295 UART0_clk, UART1_clk); 1296#endif 1297 /* Setup CPU clocks */ 1298 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1299 /* Setup PLB clock */ 1300 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1301 /* Setup OPB clock */ 1302 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1303 /* Setup external clock */ 1304 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1305 /* Setup MAL clock */ 1306 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1307 /* Setup PCI clock */ 1308 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1309 /* Setup UART0 clock */ 1310 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1311 /* Setup UART1 clock */ 1312 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1313} 1314 1315static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1316{ 1317 ppc405ep_cpc_t *cpc; 1318 uint32_t ret; 1319 1320 cpc = opaque; 1321 switch (dcrn) { 1322 case PPC405EP_CPC0_BOOT: 1323 ret = cpc->boot; 1324 break; 1325 case PPC405EP_CPC0_EPCTL: 1326 ret = cpc->epctl; 1327 break; 1328 case PPC405EP_CPC0_PLLMR0: 1329 ret = cpc->pllmr[0]; 1330 break; 1331 case PPC405EP_CPC0_PLLMR1: 1332 ret = cpc->pllmr[1]; 1333 break; 1334 case PPC405EP_CPC0_UCR: 1335 ret = cpc->ucr; 1336 break; 1337 case PPC405EP_CPC0_SRR: 1338 ret = cpc->srr; 1339 break; 1340 case PPC405EP_CPC0_JTAGID: 1341 ret = cpc->jtagid; 1342 break; 1343 case PPC405EP_CPC0_PCI: 1344 ret = cpc->pci; 1345 break; 1346 default: 1347 /* Avoid gcc warning */ 1348 ret = 0; 1349 break; 1350 } 1351 1352 return ret; 1353} 1354 1355static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1356{ 1357 ppc405ep_cpc_t *cpc; 1358 1359 cpc = opaque; 1360 switch (dcrn) { 1361 case PPC405EP_CPC0_BOOT: 1362 /* Read-only register */ 1363 break; 1364 case PPC405EP_CPC0_EPCTL: 1365 /* Don't care for now */ 1366 cpc->epctl = val & 0xC00000F3; 1367 break; 1368 case PPC405EP_CPC0_PLLMR0: 1369 cpc->pllmr[0] = val & 0x00633333; 1370 ppc405ep_compute_clocks(cpc); 1371 break; 1372 case PPC405EP_CPC0_PLLMR1: 1373 cpc->pllmr[1] = val & 0xC0F73FFF; 1374 ppc405ep_compute_clocks(cpc); 1375 break; 1376 case PPC405EP_CPC0_UCR: 1377 /* UART control - don't care for now */ 1378 cpc->ucr = val & 0x003F7F7F; 1379 break; 1380 case PPC405EP_CPC0_SRR: 1381 cpc->srr = val; 1382 break; 1383 case PPC405EP_CPC0_JTAGID: 1384 /* Read-only */ 1385 break; 1386 case PPC405EP_CPC0_PCI: 1387 cpc->pci = val; 1388 break; 1389 } 1390} 1391 1392static void ppc405ep_cpc_reset (void *opaque) 1393{ 1394 ppc405ep_cpc_t *cpc = opaque; 1395 1396 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1397 cpc->epctl = 0x00000000; 1398 cpc->pllmr[0] = 0x00011010; 1399 cpc->pllmr[1] = 0x40000000; 1400 cpc->ucr = 0x00000000; 1401 cpc->srr = 0x00040000; 1402 cpc->pci = 0x00000000; 1403 cpc->er = 0x00000000; 1404 cpc->fr = 0x00000000; 1405 cpc->sr = 0x00000000; 1406 ppc405ep_compute_clocks(cpc); 1407} 1408 1409/* XXX: sysclk should be between 25 and 100 MHz */ 1410static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1411 uint32_t sysclk) 1412{ 1413 ppc405ep_cpc_t *cpc; 1414 1415 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 1416 memcpy(cpc->clk_setup, clk_setup, 1417 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1418 cpc->jtagid = 0x20267049; 1419 cpc->sysclk = sysclk; 1420 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1421 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1422 &dcr_read_epcpc, &dcr_write_epcpc); 1423 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1424 &dcr_read_epcpc, &dcr_write_epcpc); 1425 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1426 &dcr_read_epcpc, &dcr_write_epcpc); 1427 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1428 &dcr_read_epcpc, &dcr_write_epcpc); 1429 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1430 &dcr_read_epcpc, &dcr_write_epcpc); 1431 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1432 &dcr_read_epcpc, &dcr_write_epcpc); 1433 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1434 &dcr_read_epcpc, &dcr_write_epcpc); 1435 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1436 &dcr_read_epcpc, &dcr_write_epcpc); 1437#if 0 1438 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1439 &dcr_read_epcpc, &dcr_write_epcpc); 1440 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1441 &dcr_read_epcpc, &dcr_write_epcpc); 1442 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1443 &dcr_read_epcpc, &dcr_write_epcpc); 1444#endif 1445} 1446 1447CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, 1448 MemoryRegion ram_memories[2], 1449 hwaddr ram_bases[2], 1450 hwaddr ram_sizes[2], 1451 uint32_t sysclk, DeviceState **uicdevp, 1452 int do_init) 1453{ 1454 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1455 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1456 PowerPCCPU *cpu; 1457 CPUPPCState *env; 1458 DeviceState *uicdev; 1459 SysBusDevice *uicsbd; 1460 1461 memset(clk_setup, 0, sizeof(clk_setup)); 1462 /* init CPUs */ 1463 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1464 &clk_setup[PPC405EP_CPU_CLK], 1465 &tlb_clk_setup, sysclk); 1466 env = &cpu->env; 1467 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1468 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1469 /* Internal devices init */ 1470 /* Memory mapped devices registers */ 1471 /* PLB arbitrer */ 1472 ppc4xx_plb_init(env); 1473 /* PLB to OPB bridge */ 1474 ppc4xx_pob_init(env); 1475 /* OBP arbitrer */ 1476 ppc4xx_opba_init(0xef600600); 1477 /* Initialize timers */ 1478 ppc_booke_timers_init(cpu, sysclk, 0); 1479 /* Universal interrupt controller */ 1480 uicdev = qdev_new(TYPE_PPC_UIC); 1481 uicsbd = SYS_BUS_DEVICE(uicdev); 1482 1483 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), 1484 &error_fatal); 1485 sysbus_realize_and_unref(uicsbd, &error_fatal); 1486 1487 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 1488 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 1489 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 1490 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 1491 1492 *uicdevp = uicdev; 1493 1494 /* SDRAM controller */ 1495 /* XXX 405EP has no ECC interrupt */ 1496 ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories, 1497 ram_bases, ram_sizes, do_init); 1498 /* External bus controller */ 1499 ppc405_ebc_init(env); 1500 /* DMA controller */ 1501 dma_irqs[0] = qdev_get_gpio_in(uicdev, 5); 1502 dma_irqs[1] = qdev_get_gpio_in(uicdev, 6); 1503 dma_irqs[2] = qdev_get_gpio_in(uicdev, 7); 1504 dma_irqs[3] = qdev_get_gpio_in(uicdev, 8); 1505 ppc405_dma_init(env, dma_irqs); 1506 /* IIC controller */ 1507 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, 1508 qdev_get_gpio_in(uicdev, 2)); 1509 /* GPIO */ 1510 ppc405_gpio_init(0xef600700); 1511 /* Serial ports */ 1512 if (serial_hd(0) != NULL) { 1513 serial_mm_init(address_space_mem, 0xef600300, 0, 1514 qdev_get_gpio_in(uicdev, 0), 1515 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1516 DEVICE_BIG_ENDIAN); 1517 } 1518 if (serial_hd(1) != NULL) { 1519 serial_mm_init(address_space_mem, 0xef600400, 0, 1520 qdev_get_gpio_in(uicdev, 1), 1521 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1522 DEVICE_BIG_ENDIAN); 1523 } 1524 /* OCM */ 1525 ppc405_ocm_init(env); 1526 /* GPT */ 1527 gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19); 1528 gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20); 1529 gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21); 1530 gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22); 1531 gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23); 1532 ppc4xx_gpt_init(0xef600000, gpt_irqs); 1533 /* PCI */ 1534 /* Uses UIC IRQs 3, 16, 18 */ 1535 /* MAL */ 1536 mal_irqs[0] = qdev_get_gpio_in(uicdev, 11); 1537 mal_irqs[1] = qdev_get_gpio_in(uicdev, 12); 1538 mal_irqs[2] = qdev_get_gpio_in(uicdev, 13); 1539 mal_irqs[3] = qdev_get_gpio_in(uicdev, 14); 1540 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1541 /* Ethernet */ 1542 /* Uses UIC IRQs 9, 15, 17 */ 1543 /* CPU control */ 1544 ppc405ep_cpc_init(env, clk_setup, sysclk); 1545 1546 return env; 1547}