ppc440_bamboo.c (10312B)
1/* 2 * QEMU PowerPC 440 Bamboo board emulation 3 * 4 * Copyright 2007 IBM Corporation. 5 * Authors: 6 * Jerone Young <jyoung5@us.ibm.com> 7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> 8 * Hollis Blanchard <hollisb@us.ibm.com> 9 * 10 * This work is licensed under the GNU GPL license version 2 or later. 11 * 12 */ 13 14#include "qemu/osdep.h" 15#include "qemu/units.h" 16#include "qemu/error-report.h" 17#include "qemu-common.h" 18#include "qemu/datadir.h" 19#include "qemu/error-report.h" 20#include "net/net.h" 21#include "hw/pci/pci.h" 22#include "hw/boards.h" 23#include "sysemu/kvm.h" 24#include "kvm_ppc.h" 25#include "sysemu/device_tree.h" 26#include "hw/loader.h" 27#include "elf.h" 28#include "hw/char/serial.h" 29#include "hw/ppc/ppc.h" 30#include "ppc405.h" 31#include "sysemu/sysemu.h" 32#include "sysemu/reset.h" 33#include "hw/sysbus.h" 34#include "hw/intc/ppc-uic.h" 35#include "hw/qdev-properties.h" 36#include "qapi/error.h" 37 38#define BINARY_DEVICE_TREE_FILE "bamboo.dtb" 39 40/* from u-boot */ 41#define KERNEL_ADDR 0x1000000 42#define FDT_ADDR 0x1800000 43#define RAMDISK_ADDR 0x1900000 44 45#define PPC440EP_PCI_CONFIG 0xeec00000 46#define PPC440EP_PCI_INTACK 0xeed00000 47#define PPC440EP_PCI_SPECIAL 0xeed00000 48#define PPC440EP_PCI_REGS 0xef400000 49#define PPC440EP_PCI_IO 0xe8000000 50#define PPC440EP_PCI_IOLEN 0x00010000 51 52#define PPC440EP_SDRAM_NR_BANKS 4 53 54static const ram_addr_t ppc440ep_sdram_bank_sizes[] = { 55 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0 56}; 57 58static hwaddr entry; 59 60static int bamboo_load_device_tree(hwaddr addr, 61 uint32_t ramsize, 62 hwaddr initrd_base, 63 hwaddr initrd_size, 64 const char *kernel_cmdline) 65{ 66 int ret = -1; 67 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) }; 68 char *filename; 69 int fdt_size; 70 void *fdt; 71 uint32_t tb_freq = 400000000; 72 uint32_t clock_freq = 400000000; 73 74 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 75 if (!filename) { 76 return -1; 77 } 78 fdt = load_device_tree(filename, &fdt_size); 79 g_free(filename); 80 if (fdt == NULL) { 81 return -1; 82 } 83 84 /* Manipulate device tree in memory. */ 85 86 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 87 sizeof(mem_reg_property)); 88 if (ret < 0) 89 fprintf(stderr, "couldn't set /memory/reg\n"); 90 91 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 92 initrd_base); 93 if (ret < 0) 94 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 95 96 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 97 (initrd_base + initrd_size)); 98 if (ret < 0) 99 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 100 101 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 102 kernel_cmdline); 103 if (ret < 0) 104 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 105 106 /* Copy data from the host device tree into the guest. Since the guest can 107 * directly access the timebase without host involvement, we must expose 108 * the correct frequencies. */ 109 if (kvm_enabled()) { 110 tb_freq = kvmppc_get_tbfreq(); 111 clock_freq = kvmppc_get_clockfreq(); 112 } 113 114 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency", 115 clock_freq); 116 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency", 117 tb_freq); 118 119 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 120 g_free(fdt); 121 return 0; 122} 123 124/* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 125static void mmubooke_create_initial_mapping(CPUPPCState *env, 126 target_ulong va, 127 hwaddr pa) 128{ 129 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 130 131 tlb->attr = 0; 132 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 133 tlb->size = 1U << 31; /* up to 0x80000000 */ 134 tlb->EPN = va & TARGET_PAGE_MASK; 135 tlb->RPN = pa & TARGET_PAGE_MASK; 136 tlb->PID = 0; 137 138 tlb = &env->tlb.tlbe[1]; 139 tlb->attr = 0; 140 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 141 tlb->size = 1U << 31; /* up to 0xffffffff */ 142 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 143 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 144 tlb->PID = 0; 145} 146 147static void main_cpu_reset(void *opaque) 148{ 149 PowerPCCPU *cpu = opaque; 150 CPUPPCState *env = &cpu->env; 151 152 cpu_reset(CPU(cpu)); 153 env->gpr[1] = (16 * MiB) - 8; 154 env->gpr[3] = FDT_ADDR; 155 env->nip = entry; 156 157 /* Create a mapping for the kernel. */ 158 mmubooke_create_initial_mapping(env, 0, 0); 159} 160 161static void bamboo_init(MachineState *machine) 162{ 163 const char *kernel_filename = machine->kernel_filename; 164 const char *kernel_cmdline = machine->kernel_cmdline; 165 const char *initrd_filename = machine->initrd_filename; 166 unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 }; 167 MemoryRegion *address_space_mem = get_system_memory(); 168 MemoryRegion *isa = g_new(MemoryRegion, 1); 169 MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS); 170 hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS]; 171 hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS]; 172 PCIBus *pcibus; 173 PowerPCCPU *cpu; 174 CPUPPCState *env; 175 target_long initrd_size = 0; 176 DeviceState *dev; 177 DeviceState *uicdev; 178 SysBusDevice *uicsbd; 179 int success; 180 int i; 181 182 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 183 env = &cpu->env; 184 185 if (env->mmu_model != POWERPC_MMU_BOOKE) { 186 error_report("MMU model %i not supported by this machine", 187 env->mmu_model); 188 exit(1); 189 } 190 191 qemu_register_reset(main_cpu_reset, cpu); 192 ppc_booke_timers_init(cpu, 400000000, 0); 193 ppc_dcr_init(env, NULL, NULL); 194 195 /* interrupt controller */ 196 uicdev = qdev_new(TYPE_PPC_UIC); 197 uicsbd = SYS_BUS_DEVICE(uicdev); 198 199 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), 200 &error_fatal); 201 sysbus_realize_and_unref(uicsbd, &error_fatal); 202 203 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 204 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 205 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 206 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 207 208 /* SDRAM controller */ 209 memset(ram_bases, 0, sizeof(ram_bases)); 210 memset(ram_sizes, 0, sizeof(ram_sizes)); 211 ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, 212 ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); 213 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ 214 ppc4xx_sdram_init(env, 215 qdev_get_gpio_in(uicdev, 14), 216 PPC440EP_SDRAM_NR_BANKS, ram_memories, 217 ram_bases, ram_sizes, 1); 218 219 /* PCI */ 220 dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE, 221 PPC440EP_PCI_CONFIG, 222 qdev_get_gpio_in(uicdev, pci_irq_nrs[0]), 223 qdev_get_gpio_in(uicdev, pci_irq_nrs[1]), 224 qdev_get_gpio_in(uicdev, pci_irq_nrs[2]), 225 qdev_get_gpio_in(uicdev, pci_irq_nrs[3]), 226 NULL); 227 pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 228 if (!pcibus) { 229 error_report("couldn't create PCI controller"); 230 exit(1); 231 } 232 233 memory_region_init_alias(isa, NULL, "isa_mmio", 234 get_system_io(), 0, PPC440EP_PCI_IOLEN); 235 memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); 236 237 if (serial_hd(0) != NULL) { 238 serial_mm_init(address_space_mem, 0xef600300, 0, 239 qdev_get_gpio_in(uicdev, 0), 240 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 241 DEVICE_BIG_ENDIAN); 242 } 243 if (serial_hd(1) != NULL) { 244 serial_mm_init(address_space_mem, 0xef600400, 0, 245 qdev_get_gpio_in(uicdev, 1), 246 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 247 DEVICE_BIG_ENDIAN); 248 } 249 250 if (pcibus) { 251 /* Register network interfaces. */ 252 for (i = 0; i < nb_nics; i++) { 253 /* There are no PCI NICs on the Bamboo board, but there are 254 * PCI slots, so we can pick whatever default model we want. */ 255 pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); 256 } 257 } 258 259 /* Load kernel. */ 260 if (kernel_filename) { 261 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 262 success = load_uimage(kernel_filename, &entry, &loadaddr, NULL, 263 NULL, NULL); 264 if (success < 0) { 265 uint64_t elf_entry; 266 success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 267 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 268 entry = elf_entry; 269 } 270 /* XXX try again as binary */ 271 if (success < 0) { 272 error_report("could not load kernel '%s'", kernel_filename); 273 exit(1); 274 } 275 } 276 277 /* Load initrd. */ 278 if (initrd_filename) { 279 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, 280 machine->ram_size - RAMDISK_ADDR); 281 282 if (initrd_size < 0) { 283 error_report("could not load ram disk '%s' at %x", 284 initrd_filename, RAMDISK_ADDR); 285 exit(1); 286 } 287 } 288 289 /* If we're loading a kernel directly, we must load the device tree too. */ 290 if (kernel_filename) { 291 if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, 292 initrd_size, kernel_cmdline) < 0) { 293 error_report("couldn't load device tree"); 294 exit(1); 295 } 296 } 297} 298 299static void bamboo_machine_init(MachineClass *mc) 300{ 301 mc->desc = "bamboo"; 302 mc->init = bamboo_init; 303 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); 304 mc->default_ram_id = "ppc4xx.sdram"; 305} 306 307DEFINE_MACHINE("bamboo", bamboo_machine_init)