spapr_pci.c (81716B)
1/* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26#include "qemu/osdep.h" 27#include "qapi/error.h" 28#include "hw/irq.h" 29#include "hw/sysbus.h" 30#include "migration/vmstate.h" 31#include "hw/pci/pci.h" 32#include "hw/pci/msi.h" 33#include "hw/pci/msix.h" 34#include "hw/pci/pci_host.h" 35#include "hw/ppc/spapr.h" 36#include "hw/pci-host/spapr.h" 37#include "exec/ram_addr.h" 38#include <libfdt.h> 39#include "trace.h" 40#include "qemu/error-report.h" 41#include "qemu/module.h" 42#include "qapi/qmp/qerror.h" 43#include "hw/ppc/fdt.h" 44#include "hw/pci/pci_bridge.h" 45#include "hw/pci/pci_bus.h" 46#include "hw/pci/pci_ids.h" 47#include "hw/ppc/spapr_drc.h" 48#include "hw/qdev-properties.h" 49#include "sysemu/device_tree.h" 50#include "sysemu/kvm.h" 51#include "sysemu/hostmem.h" 52#include "sysemu/numa.h" 53#include "hw/ppc/spapr_numa.h" 54#include "qemu/log.h" 55 56/* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 57#define RTAS_QUERY_FN 0 58#define RTAS_CHANGE_FN 1 59#define RTAS_RESET_FN 2 60#define RTAS_CHANGE_MSI_FN 3 61#define RTAS_CHANGE_MSIX_FN 4 62 63/* Interrupt types to return on RTAS_CHANGE_* */ 64#define RTAS_TYPE_MSI 1 65#define RTAS_TYPE_MSIX 2 66 67SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) 68{ 69 SpaprPhbState *sphb; 70 71 QLIST_FOREACH(sphb, &spapr->phbs, list) { 72 if (sphb->buid != buid) { 73 continue; 74 } 75 return sphb; 76 } 77 78 return NULL; 79} 80 81PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, 82 uint32_t config_addr) 83{ 84 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); 85 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 86 int bus_num = (config_addr >> 16) & 0xFF; 87 int devfn = (config_addr >> 8) & 0xFF; 88 89 if (!phb) { 90 return NULL; 91 } 92 93 return pci_find_device(phb->bus, bus_num, devfn); 94} 95 96static uint32_t rtas_pci_cfgaddr(uint32_t arg) 97{ 98 /* This handles the encoding of extended config space addresses */ 99 return ((arg >> 20) & 0xf00) | (arg & 0xff); 100} 101 102static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, 103 uint32_t addr, uint32_t size, 104 target_ulong rets) 105{ 106 PCIDevice *pci_dev; 107 uint32_t val; 108 109 if ((size != 1) && (size != 2) && (size != 4)) { 110 /* access must be 1, 2 or 4 bytes */ 111 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 112 return; 113 } 114 115 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 116 addr = rtas_pci_cfgaddr(addr); 117 118 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 119 /* Access must be to a valid device, within bounds and 120 * naturally aligned */ 121 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 122 return; 123 } 124 125 val = pci_host_config_read_common(pci_dev, addr, 126 pci_config_size(pci_dev), size); 127 128 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 129 rtas_st(rets, 1, val); 130} 131 132static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 133 uint32_t token, uint32_t nargs, 134 target_ulong args, 135 uint32_t nret, target_ulong rets) 136{ 137 uint64_t buid; 138 uint32_t size, addr; 139 140 if ((nargs != 4) || (nret != 2)) { 141 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 142 return; 143 } 144 145 buid = rtas_ldq(args, 1); 146 size = rtas_ld(args, 3); 147 addr = rtas_ld(args, 0); 148 149 finish_read_pci_config(spapr, buid, addr, size, rets); 150} 151 152static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 153 uint32_t token, uint32_t nargs, 154 target_ulong args, 155 uint32_t nret, target_ulong rets) 156{ 157 uint32_t size, addr; 158 159 if ((nargs != 2) || (nret != 2)) { 160 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 161 return; 162 } 163 164 size = rtas_ld(args, 1); 165 addr = rtas_ld(args, 0); 166 167 finish_read_pci_config(spapr, 0, addr, size, rets); 168} 169 170static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, 171 uint32_t addr, uint32_t size, 172 uint32_t val, target_ulong rets) 173{ 174 PCIDevice *pci_dev; 175 176 if ((size != 1) && (size != 2) && (size != 4)) { 177 /* access must be 1, 2 or 4 bytes */ 178 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 179 return; 180 } 181 182 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 183 addr = rtas_pci_cfgaddr(addr); 184 185 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 186 /* Access must be to a valid device, within bounds and 187 * naturally aligned */ 188 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 189 return; 190 } 191 192 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 193 val, size); 194 195 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 196} 197 198static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 199 uint32_t token, uint32_t nargs, 200 target_ulong args, 201 uint32_t nret, target_ulong rets) 202{ 203 uint64_t buid; 204 uint32_t val, size, addr; 205 206 if ((nargs != 5) || (nret != 1)) { 207 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 208 return; 209 } 210 211 buid = rtas_ldq(args, 1); 212 val = rtas_ld(args, 4); 213 size = rtas_ld(args, 3); 214 addr = rtas_ld(args, 0); 215 216 finish_write_pci_config(spapr, buid, addr, size, val, rets); 217} 218 219static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 220 uint32_t token, uint32_t nargs, 221 target_ulong args, 222 uint32_t nret, target_ulong rets) 223{ 224 uint32_t val, size, addr; 225 226 if ((nargs != 3) || (nret != 1)) { 227 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 228 return; 229 } 230 231 232 val = rtas_ld(args, 2); 233 size = rtas_ld(args, 1); 234 addr = rtas_ld(args, 0); 235 236 finish_write_pci_config(spapr, 0, addr, size, val, rets); 237} 238 239/* 240 * Set MSI/MSIX message data. 241 * This is required for msi_notify()/msix_notify() which 242 * will write at the addresses via spapr_msi_write(). 243 * 244 * If hwaddr == 0, all entries will have .data == first_irq i.e. 245 * table will be reset. 246 */ 247static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 248 unsigned first_irq, unsigned req_num) 249{ 250 unsigned i; 251 MSIMessage msg = { .address = addr, .data = first_irq }; 252 253 if (!msix) { 254 msi_set_message(pdev, msg); 255 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 256 return; 257 } 258 259 for (i = 0; i < req_num; ++i) { 260 msix_set_message(pdev, i, msg); 261 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 262 if (addr) { 263 ++msg.data; 264 } 265 } 266} 267 268static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, 269 uint32_t token, uint32_t nargs, 270 target_ulong args, uint32_t nret, 271 target_ulong rets) 272{ 273 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 274 uint32_t config_addr = rtas_ld(args, 0); 275 uint64_t buid = rtas_ldq(args, 1); 276 unsigned int func = rtas_ld(args, 3); 277 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 278 unsigned int seq_num = rtas_ld(args, 5); 279 unsigned int ret_intr_type; 280 unsigned int irq, max_irqs = 0; 281 SpaprPhbState *phb = NULL; 282 PCIDevice *pdev = NULL; 283 SpaprPciMsi *msi; 284 int *config_addr_key; 285 Error *err = NULL; 286 int i; 287 288 /* Fins SpaprPhbState */ 289 phb = spapr_pci_find_phb(spapr, buid); 290 if (phb) { 291 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 292 } 293 if (!phb || !pdev) { 294 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 295 return; 296 } 297 298 switch (func) { 299 case RTAS_CHANGE_FN: 300 if (msi_present(pdev)) { 301 ret_intr_type = RTAS_TYPE_MSI; 302 } else if (msix_present(pdev)) { 303 ret_intr_type = RTAS_TYPE_MSIX; 304 } else { 305 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 306 return; 307 } 308 break; 309 case RTAS_CHANGE_MSI_FN: 310 if (msi_present(pdev)) { 311 ret_intr_type = RTAS_TYPE_MSI; 312 } else { 313 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 314 return; 315 } 316 break; 317 case RTAS_CHANGE_MSIX_FN: 318 if (msix_present(pdev)) { 319 ret_intr_type = RTAS_TYPE_MSIX; 320 } else { 321 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 322 return; 323 } 324 break; 325 default: 326 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 327 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 328 return; 329 } 330 331 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 332 333 /* Releasing MSIs */ 334 if (!req_num) { 335 if (!msi) { 336 trace_spapr_pci_msi("Releasing wrong config", config_addr); 337 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 338 return; 339 } 340 341 if (msi_present(pdev)) { 342 spapr_msi_setmsg(pdev, 0, false, 0, 0); 343 } 344 if (msix_present(pdev)) { 345 spapr_msi_setmsg(pdev, 0, true, 0, 0); 346 } 347 g_hash_table_remove(phb->msi, &config_addr); 348 349 trace_spapr_pci_msi("Released MSIs", config_addr); 350 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 351 rtas_st(rets, 1, 0); 352 return; 353 } 354 355 /* Enabling MSI */ 356 357 /* Check if the device supports as many IRQs as requested */ 358 if (ret_intr_type == RTAS_TYPE_MSI) { 359 max_irqs = msi_nr_vectors_allocated(pdev); 360 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 361 max_irqs = pdev->msix_entries_nr; 362 } 363 if (!max_irqs) { 364 error_report("Requested interrupt type %d is not enabled for device %x", 365 ret_intr_type, config_addr); 366 rtas_st(rets, 0, -1); /* Hardware error */ 367 return; 368 } 369 /* Correct the number if the guest asked for too many */ 370 if (req_num > max_irqs) { 371 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 372 req_num = max_irqs; 373 irq = 0; /* to avoid misleading trace */ 374 goto out; 375 } 376 377 /* Allocate MSIs */ 378 if (smc->legacy_irq_allocation) { 379 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, 380 &err); 381 } else { 382 irq = spapr_irq_msi_alloc(spapr, req_num, 383 ret_intr_type == RTAS_TYPE_MSI, &err); 384 } 385 if (err) { 386 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 387 config_addr); 388 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 389 return; 390 } 391 392 for (i = 0; i < req_num; i++) { 393 spapr_irq_claim(spapr, irq + i, false, &err); 394 if (err) { 395 if (i) { 396 spapr_irq_free(spapr, irq, i); 397 } 398 if (!smc->legacy_irq_allocation) { 399 spapr_irq_msi_free(spapr, irq, req_num); 400 } 401 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 402 config_addr); 403 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 404 return; 405 } 406 } 407 408 /* Release previous MSIs */ 409 if (msi) { 410 g_hash_table_remove(phb->msi, &config_addr); 411 } 412 413 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 414 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 415 irq, req_num); 416 417 /* Add MSI device to cache */ 418 msi = g_new(SpaprPciMsi, 1); 419 msi->first_irq = irq; 420 msi->num = req_num; 421 config_addr_key = g_new(int, 1); 422 *config_addr_key = config_addr; 423 g_hash_table_insert(phb->msi, config_addr_key, msi); 424 425out: 426 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 427 rtas_st(rets, 1, req_num); 428 rtas_st(rets, 2, ++seq_num); 429 if (nret > 3) { 430 rtas_st(rets, 3, ret_intr_type); 431 } 432 433 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 434} 435 436static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 437 SpaprMachineState *spapr, 438 uint32_t token, 439 uint32_t nargs, 440 target_ulong args, 441 uint32_t nret, 442 target_ulong rets) 443{ 444 uint32_t config_addr = rtas_ld(args, 0); 445 uint64_t buid = rtas_ldq(args, 1); 446 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 447 SpaprPhbState *phb = NULL; 448 PCIDevice *pdev = NULL; 449 SpaprPciMsi *msi; 450 451 /* Find SpaprPhbState */ 452 phb = spapr_pci_find_phb(spapr, buid); 453 if (phb) { 454 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 455 } 456 if (!phb || !pdev) { 457 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 458 return; 459 } 460 461 /* Find device descriptor and start IRQ */ 462 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr); 463 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 464 trace_spapr_pci_msi("Failed to return vector", config_addr); 465 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 466 return; 467 } 468 intr_src_num = msi->first_irq + ioa_intr_num; 469 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 470 intr_src_num); 471 472 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 473 rtas_st(rets, 1, intr_src_num); 474 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 475} 476 477static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 478 SpaprMachineState *spapr, 479 uint32_t token, uint32_t nargs, 480 target_ulong args, uint32_t nret, 481 target_ulong rets) 482{ 483 SpaprPhbState *sphb; 484 uint32_t addr, option; 485 uint64_t buid; 486 int ret; 487 488 if ((nargs != 4) || (nret != 1)) { 489 goto param_error_exit; 490 } 491 492 buid = rtas_ldq(args, 1); 493 addr = rtas_ld(args, 0); 494 option = rtas_ld(args, 3); 495 496 sphb = spapr_pci_find_phb(spapr, buid); 497 if (!sphb) { 498 goto param_error_exit; 499 } 500 501 if (!spapr_phb_eeh_available(sphb)) { 502 goto param_error_exit; 503 } 504 505 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); 506 rtas_st(rets, 0, ret); 507 return; 508 509param_error_exit: 510 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 511} 512 513static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 514 SpaprMachineState *spapr, 515 uint32_t token, uint32_t nargs, 516 target_ulong args, uint32_t nret, 517 target_ulong rets) 518{ 519 SpaprPhbState *sphb; 520 PCIDevice *pdev; 521 uint32_t addr, option; 522 uint64_t buid; 523 524 if ((nargs != 4) || (nret != 2)) { 525 goto param_error_exit; 526 } 527 528 buid = rtas_ldq(args, 1); 529 sphb = spapr_pci_find_phb(spapr, buid); 530 if (!sphb) { 531 goto param_error_exit; 532 } 533 534 if (!spapr_phb_eeh_available(sphb)) { 535 goto param_error_exit; 536 } 537 538 /* 539 * We always have PE address of form "00BB0001". "BB" 540 * represents the bus number of PE's primary bus. 541 */ 542 option = rtas_ld(args, 3); 543 switch (option) { 544 case RTAS_GET_PE_ADDR: 545 addr = rtas_ld(args, 0); 546 pdev = spapr_pci_find_dev(spapr, buid, addr); 547 if (!pdev) { 548 goto param_error_exit; 549 } 550 551 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); 552 break; 553 case RTAS_GET_PE_MODE: 554 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 555 break; 556 default: 557 goto param_error_exit; 558 } 559 560 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 561 return; 562 563param_error_exit: 564 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 565} 566 567static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 568 SpaprMachineState *spapr, 569 uint32_t token, uint32_t nargs, 570 target_ulong args, uint32_t nret, 571 target_ulong rets) 572{ 573 SpaprPhbState *sphb; 574 uint64_t buid; 575 int state, ret; 576 577 if ((nargs != 3) || (nret != 4 && nret != 5)) { 578 goto param_error_exit; 579 } 580 581 buid = rtas_ldq(args, 1); 582 sphb = spapr_pci_find_phb(spapr, buid); 583 if (!sphb) { 584 goto param_error_exit; 585 } 586 587 if (!spapr_phb_eeh_available(sphb)) { 588 goto param_error_exit; 589 } 590 591 ret = spapr_phb_vfio_eeh_get_state(sphb, &state); 592 rtas_st(rets, 0, ret); 593 if (ret != RTAS_OUT_SUCCESS) { 594 return; 595 } 596 597 rtas_st(rets, 1, state); 598 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 599 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 600 if (nret >= 5) { 601 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 602 } 603 return; 604 605param_error_exit: 606 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 607} 608 609static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 610 SpaprMachineState *spapr, 611 uint32_t token, uint32_t nargs, 612 target_ulong args, uint32_t nret, 613 target_ulong rets) 614{ 615 SpaprPhbState *sphb; 616 uint32_t option; 617 uint64_t buid; 618 int ret; 619 620 if ((nargs != 4) || (nret != 1)) { 621 goto param_error_exit; 622 } 623 624 buid = rtas_ldq(args, 1); 625 option = rtas_ld(args, 3); 626 sphb = spapr_pci_find_phb(spapr, buid); 627 if (!sphb) { 628 goto param_error_exit; 629 } 630 631 if (!spapr_phb_eeh_available(sphb)) { 632 goto param_error_exit; 633 } 634 635 ret = spapr_phb_vfio_eeh_reset(sphb, option); 636 rtas_st(rets, 0, ret); 637 return; 638 639param_error_exit: 640 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 641} 642 643static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 644 SpaprMachineState *spapr, 645 uint32_t token, uint32_t nargs, 646 target_ulong args, uint32_t nret, 647 target_ulong rets) 648{ 649 SpaprPhbState *sphb; 650 uint64_t buid; 651 int ret; 652 653 if ((nargs != 3) || (nret != 1)) { 654 goto param_error_exit; 655 } 656 657 buid = rtas_ldq(args, 1); 658 sphb = spapr_pci_find_phb(spapr, buid); 659 if (!sphb) { 660 goto param_error_exit; 661 } 662 663 if (!spapr_phb_eeh_available(sphb)) { 664 goto param_error_exit; 665 } 666 667 ret = spapr_phb_vfio_eeh_configure(sphb); 668 rtas_st(rets, 0, ret); 669 return; 670 671param_error_exit: 672 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 673} 674 675/* To support it later */ 676static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 677 SpaprMachineState *spapr, 678 uint32_t token, uint32_t nargs, 679 target_ulong args, uint32_t nret, 680 target_ulong rets) 681{ 682 SpaprPhbState *sphb; 683 int option; 684 uint64_t buid; 685 686 if ((nargs != 8) || (nret != 1)) { 687 goto param_error_exit; 688 } 689 690 buid = rtas_ldq(args, 1); 691 sphb = spapr_pci_find_phb(spapr, buid); 692 if (!sphb) { 693 goto param_error_exit; 694 } 695 696 if (!spapr_phb_eeh_available(sphb)) { 697 goto param_error_exit; 698 } 699 700 option = rtas_ld(args, 7); 701 switch (option) { 702 case RTAS_SLOT_TEMP_ERR_LOG: 703 case RTAS_SLOT_PERM_ERR_LOG: 704 break; 705 default: 706 goto param_error_exit; 707 } 708 709 /* We don't have error log yet */ 710 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 711 return; 712 713param_error_exit: 714 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 715} 716 717static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 718{ 719 /* 720 * Here we use the number returned by pci_swizzle_map_irq_fn to find a 721 * corresponding qemu_irq. 722 */ 723 SpaprPhbState *phb = opaque; 724 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 725 726 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 727 qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level); 728} 729 730static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 731{ 732 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 733 PCIINTxRoute route; 734 735 route.mode = PCI_INTX_ENABLED; 736 route.irq = sphb->lsi_table[pin].irq; 737 738 return route; 739} 740 741static uint64_t spapr_msi_read(void *opaque, hwaddr addr, unsigned size) 742{ 743 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid access\n", __func__); 744 return 0; 745} 746 747/* 748 * MSI/MSIX memory region implementation. 749 * The handler handles both MSI and MSIX. 750 * The vector number is encoded in least bits in data. 751 */ 752static void spapr_msi_write(void *opaque, hwaddr addr, 753 uint64_t data, unsigned size) 754{ 755 SpaprMachineState *spapr = opaque; 756 uint32_t irq = data; 757 758 trace_spapr_pci_msi_write(addr, data, irq); 759 760 qemu_irq_pulse(spapr_qirq(spapr, irq)); 761} 762 763static const MemoryRegionOps spapr_msi_ops = { 764 /* 765 * .read result is undefined by PCI spec. 766 * define .read method to avoid assert failure in memory_region_init_io 767 */ 768 .read = spapr_msi_read, 769 .write = spapr_msi_write, 770 .endianness = DEVICE_LITTLE_ENDIAN 771}; 772 773/* 774 * PHB PCI device 775 */ 776static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 777{ 778 SpaprPhbState *phb = opaque; 779 780 return &phb->iommu_as; 781} 782 783static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 784{ 785 g_autofree char *path = NULL; 786 g_autofree char *host = NULL; 787 g_autofree char *devspec = NULL; 788 char *buf = NULL; 789 790 /* Get the PCI VFIO host id */ 791 host = object_property_get_str(OBJECT(pdev), "host", NULL); 792 if (!host) { 793 return NULL; 794 } 795 796 /* Construct the path of the file that will give us the DT location */ 797 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 798 if (!g_file_get_contents(path, &devspec, NULL, NULL)) { 799 return NULL; 800 } 801 802 /* Construct and read from host device tree the loc-code */ 803 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", devspec); 804 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 805 return NULL; 806 } 807 return buf; 808} 809 810static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 811{ 812 char *buf; 813 const char *devtype = "qemu"; 814 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 815 816 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 817 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 818 if (buf) { 819 return buf; 820 } 821 devtype = "vfio"; 822 } 823 /* 824 * For emulated devices and VFIO-failure case, make up 825 * the loc-code. 826 */ 827 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 828 devtype, pdev->name, sphb->index, busnr, 829 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 830 return buf; 831} 832 833/* Macros to operate with address in OF binding to PCI */ 834#define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 835#define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 836#define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 837#define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 838#define b_ss(x) b_x((x), 24, 2) /* the space code */ 839#define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 840#define b_ddddd(x) b_x((x), 11, 5) /* device number */ 841#define b_fff(x) b_x((x), 8, 3) /* function number */ 842#define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 843 844/* for 'reg' OF properties */ 845#define RESOURCE_CELLS_SIZE 2 846#define RESOURCE_CELLS_ADDRESS 3 847 848typedef struct ResourceFields { 849 uint32_t phys_hi; 850 uint32_t phys_mid; 851 uint32_t phys_lo; 852 uint32_t size_hi; 853 uint32_t size_lo; 854} QEMU_PACKED ResourceFields; 855 856typedef struct ResourceProps { 857 ResourceFields reg[8]; 858 uint32_t reg_len; 859} ResourceProps; 860 861/* fill in the 'reg' OF properties for 862 * a PCI device. 'reg' describes resource requirements for a 863 * device's IO/MEM regions. 864 * 865 * the property is an array of ('phys-addr', 'size') pairs describing 866 * the addressable regions of the PCI device, where 'phys-addr' is a 867 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 868 * (phys.hi, phys.mid, phys.lo), and 'size' is a 869 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 870 * 871 * phys.hi = 0xYYXXXXZZ, where: 872 * 0xYY = npt000ss 873 * ||| | 874 * ||| +-- space code 875 * ||| | 876 * ||| + 00 if configuration space 877 * ||| + 01 if IO region, 878 * ||| + 10 if 32-bit MEM region 879 * ||| + 11 if 64-bit MEM region 880 * ||| 881 * ||+------ for non-relocatable IO: 1 if aliased 882 * || for relocatable IO: 1 if below 64KB 883 * || for MEM: 1 if below 1MB 884 * |+------- 1 if region is prefetchable 885 * +-------- 1 if region is non-relocatable 886 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 887 * bits respectively 888 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 889 * to the region 890 * 891 * phys.mid and phys.lo correspond respectively to the hi/lo portions 892 * of the actual address of the region. 893 * 894 * note also that addresses defined in this property are, at least 895 * for PAPR guests, relative to the PHBs IO/MEM windows, and 896 * correspond directly to the addresses in the BARs. 897 * 898 * in accordance with PCI Bus Binding to Open Firmware, 899 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 900 * Appendix C. 901 */ 902static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 903{ 904 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 905 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 906 b_ddddd(PCI_SLOT(d->devfn)) | 907 b_fff(PCI_FUNC(d->devfn))); 908 ResourceFields *reg; 909 int i, reg_idx = 0; 910 911 /* config space region */ 912 reg = &rp->reg[reg_idx++]; 913 reg->phys_hi = cpu_to_be32(dev_id); 914 reg->phys_mid = 0; 915 reg->phys_lo = 0; 916 reg->size_hi = 0; 917 reg->size_lo = 0; 918 919 for (i = 0; i < PCI_NUM_REGIONS; i++) { 920 if (!d->io_regions[i].size) { 921 continue; 922 } 923 924 reg = &rp->reg[reg_idx++]; 925 926 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 927 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 928 reg->phys_hi |= cpu_to_be32(b_ss(1)); 929 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 930 reg->phys_hi |= cpu_to_be32(b_ss(3)); 931 } else { 932 reg->phys_hi |= cpu_to_be32(b_ss(2)); 933 } 934 reg->phys_mid = 0; 935 reg->phys_lo = 0; 936 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 937 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 938 } 939 940 rp->reg_len = reg_idx * sizeof(ResourceFields); 941} 942 943typedef struct PCIClass PCIClass; 944typedef struct PCISubClass PCISubClass; 945typedef struct PCIIFace PCIIFace; 946 947struct PCIIFace { 948 int iface; 949 const char *name; 950}; 951 952struct PCISubClass { 953 int subclass; 954 const char *name; 955 const PCIIFace *iface; 956}; 957 958struct PCIClass { 959 const char *name; 960 const PCISubClass *subc; 961}; 962 963static const PCISubClass undef_subclass[] = { 964 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, 965 { 0xFF, NULL, NULL }, 966}; 967 968static const PCISubClass mass_subclass[] = { 969 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, 970 { PCI_CLASS_STORAGE_IDE, "ide", NULL }, 971 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, 972 { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, 973 { PCI_CLASS_STORAGE_RAID, "raid", NULL }, 974 { PCI_CLASS_STORAGE_ATA, "ata", NULL }, 975 { PCI_CLASS_STORAGE_SATA, "sata", NULL }, 976 { PCI_CLASS_STORAGE_SAS, "sas", NULL }, 977 { 0xFF, NULL, NULL }, 978}; 979 980static const PCISubClass net_subclass[] = { 981 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, 982 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, 983 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, 984 { PCI_CLASS_NETWORK_ATM, "atm", NULL }, 985 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, 986 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, 987 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, 988 { 0xFF, NULL, NULL }, 989}; 990 991static const PCISubClass displ_subclass[] = { 992 { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, 993 { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, 994 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, 995 { 0xFF, NULL, NULL }, 996}; 997 998static const PCISubClass media_subclass[] = { 999 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, 1000 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, 1001 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, 1002 { 0xFF, NULL, NULL }, 1003}; 1004 1005static const PCISubClass mem_subclass[] = { 1006 { PCI_CLASS_MEMORY_RAM, "memory", NULL }, 1007 { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, 1008 { 0xFF, NULL, NULL }, 1009}; 1010 1011static const PCISubClass bridg_subclass[] = { 1012 { PCI_CLASS_BRIDGE_HOST, "host", NULL }, 1013 { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, 1014 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, 1015 { PCI_CLASS_BRIDGE_MC, "mca", NULL }, 1016 { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, 1017 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, 1018 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, 1019 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, 1020 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, 1021 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, 1022 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, 1023 { 0xFF, NULL, NULL }, 1024}; 1025 1026static const PCISubClass comm_subclass[] = { 1027 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, 1028 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, 1029 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, 1030 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, 1031 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, 1032 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, 1033 { 0xFF, NULL, NULL, }, 1034}; 1035 1036static const PCIIFace pic_iface[] = { 1037 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, 1038 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, 1039 { 0xFF, NULL }, 1040}; 1041 1042static const PCISubClass sys_subclass[] = { 1043 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, 1044 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, 1045 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, 1046 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, 1047 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, 1048 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, 1049 { 0xFF, NULL, NULL }, 1050}; 1051 1052static const PCISubClass inp_subclass[] = { 1053 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, 1054 { PCI_CLASS_INPUT_PEN, "pen", NULL }, 1055 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, 1056 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, 1057 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, 1058 { 0xFF, NULL, NULL }, 1059}; 1060 1061static const PCISubClass dock_subclass[] = { 1062 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, 1063 { 0xFF, NULL, NULL }, 1064}; 1065 1066static const PCISubClass cpu_subclass[] = { 1067 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, 1068 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, 1069 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, 1070 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, 1071 { 0xFF, NULL, NULL }, 1072}; 1073 1074static const PCIIFace usb_iface[] = { 1075 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, 1076 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, 1077 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, 1078 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, 1079 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, 1080 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, 1081 { 0xFF, NULL }, 1082}; 1083 1084static const PCISubClass ser_subclass[] = { 1085 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, 1086 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, 1087 { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, 1088 { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, 1089 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, 1090 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, 1091 { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, 1092 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, 1093 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, 1094 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, 1095 { 0xFF, NULL, NULL }, 1096}; 1097 1098static const PCISubClass wrl_subclass[] = { 1099 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, 1100 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, 1101 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, 1102 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, 1103 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, 1104 { 0xFF, NULL, NULL }, 1105}; 1106 1107static const PCISubClass sat_subclass[] = { 1108 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, 1109 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, 1110 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, 1111 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, 1112 { 0xFF, NULL, NULL }, 1113}; 1114 1115static const PCISubClass crypt_subclass[] = { 1116 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, 1117 { PCI_CLASS_CRYPT_ENTERTAINMENT, 1118 "entertainment-encryption", NULL }, 1119 { 0xFF, NULL, NULL }, 1120}; 1121 1122static const PCISubClass spc_subclass[] = { 1123 { PCI_CLASS_SP_DPIO, "dpio", NULL }, 1124 { PCI_CLASS_SP_PERF, "counter", NULL }, 1125 { PCI_CLASS_SP_SYNCH, "measurement", NULL }, 1126 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, 1127 { 0xFF, NULL, NULL }, 1128}; 1129 1130static const PCIClass pci_classes[] = { 1131 { "legacy-device", undef_subclass }, 1132 { "mass-storage", mass_subclass }, 1133 { "network", net_subclass }, 1134 { "display", displ_subclass, }, 1135 { "multimedia-device", media_subclass }, 1136 { "memory-controller", mem_subclass }, 1137 { "unknown-bridge", bridg_subclass }, 1138 { "communication-controller", comm_subclass}, 1139 { "system-peripheral", sys_subclass }, 1140 { "input-controller", inp_subclass }, 1141 { "docking-station", dock_subclass }, 1142 { "cpu", cpu_subclass }, 1143 { "serial-bus", ser_subclass }, 1144 { "wireless-controller", wrl_subclass }, 1145 { "intelligent-io", NULL }, 1146 { "satellite-device", sat_subclass }, 1147 { "encryption", crypt_subclass }, 1148 { "data-processing-controller", spc_subclass }, 1149}; 1150 1151static const char *dt_name_from_class(uint8_t class, uint8_t subclass, 1152 uint8_t iface) 1153{ 1154 const PCIClass *pclass; 1155 const PCISubClass *psubclass; 1156 const PCIIFace *piface; 1157 const char *name; 1158 1159 if (class >= ARRAY_SIZE(pci_classes)) { 1160 return "pci"; 1161 } 1162 1163 pclass = pci_classes + class; 1164 name = pclass->name; 1165 1166 if (pclass->subc == NULL) { 1167 return name; 1168 } 1169 1170 psubclass = pclass->subc; 1171 while ((psubclass->subclass & 0xff) != 0xff) { 1172 if ((psubclass->subclass & 0xff) == subclass) { 1173 name = psubclass->name; 1174 break; 1175 } 1176 psubclass++; 1177 } 1178 1179 piface = psubclass->iface; 1180 if (piface == NULL) { 1181 return name; 1182 } 1183 while ((piface->iface & 0xff) != 0xff) { 1184 if ((piface->iface & 0xff) == iface) { 1185 name = piface->name; 1186 break; 1187 } 1188 piface++; 1189 } 1190 1191 return name; 1192} 1193 1194/* 1195 * DRC helper functions 1196 */ 1197 1198static uint32_t drc_id_from_devfn(SpaprPhbState *phb, 1199 uint8_t chassis, int32_t devfn) 1200{ 1201 return (phb->index << 16) | (chassis << 8) | devfn; 1202} 1203 1204static SpaprDrc *drc_from_devfn(SpaprPhbState *phb, 1205 uint8_t chassis, int32_t devfn) 1206{ 1207 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, 1208 drc_id_from_devfn(phb, chassis, devfn)); 1209} 1210 1211static uint8_t chassis_from_bus(PCIBus *bus) 1212{ 1213 if (pci_bus_is_root(bus)) { 1214 return 0; 1215 } else { 1216 PCIDevice *bridge = pci_bridge_get_device(bus); 1217 1218 return object_property_get_uint(OBJECT(bridge), "chassis_nr", 1219 &error_abort); 1220 } 1221} 1222 1223static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev) 1224{ 1225 uint8_t chassis = chassis_from_bus(pci_get_bus(dev)); 1226 1227 return drc_from_devfn(phb, chassis, dev->devfn); 1228} 1229 1230static void add_drcs(SpaprPhbState *phb, PCIBus *bus) 1231{ 1232 Object *owner; 1233 int i; 1234 uint8_t chassis; 1235 1236 if (!phb->dr_enabled) { 1237 return; 1238 } 1239 1240 chassis = chassis_from_bus(bus); 1241 1242 if (pci_bus_is_root(bus)) { 1243 owner = OBJECT(phb); 1244 } else { 1245 owner = OBJECT(pci_bridge_get_device(bus)); 1246 } 1247 1248 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) { 1249 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI, 1250 drc_id_from_devfn(phb, chassis, i)); 1251 } 1252} 1253 1254static void remove_drcs(SpaprPhbState *phb, PCIBus *bus) 1255{ 1256 int i; 1257 uint8_t chassis; 1258 1259 if (!phb->dr_enabled) { 1260 return; 1261 } 1262 1263 chassis = chassis_from_bus(bus); 1264 1265 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { 1266 SpaprDrc *drc = drc_from_devfn(phb, chassis, i); 1267 1268 if (drc) { 1269 object_unparent(OBJECT(drc)); 1270 } 1271 } 1272} 1273 1274typedef struct PciWalkFdt { 1275 void *fdt; 1276 int offset; 1277 SpaprPhbState *sphb; 1278 int err; 1279} PciWalkFdt; 1280 1281static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1282 void *fdt, int parent_offset); 1283 1284static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev, 1285 void *opaque) 1286{ 1287 PciWalkFdt *p = opaque; 1288 int err; 1289 1290 if (p->err) { 1291 /* Something's already broken, don't keep going */ 1292 return; 1293 } 1294 1295 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset); 1296 if (err < 0) { 1297 p->err = err; 1298 } 1299} 1300 1301/* Augment PCI device node with bridge specific information */ 1302static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus, 1303 void *fdt, int offset) 1304{ 1305 Object *owner; 1306 PciWalkFdt cbinfo = { 1307 .fdt = fdt, 1308 .offset = offset, 1309 .sphb = sphb, 1310 .err = 0, 1311 }; 1312 int ret; 1313 1314 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1315 RESOURCE_CELLS_ADDRESS)); 1316 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1317 RESOURCE_CELLS_SIZE)); 1318 1319 assert(bus); 1320 pci_for_each_device_reverse(bus, pci_bus_num(bus), 1321 spapr_dt_pci_device_cb, &cbinfo); 1322 if (cbinfo.err) { 1323 return cbinfo.err; 1324 } 1325 1326 if (pci_bus_is_root(bus)) { 1327 owner = OBJECT(sphb); 1328 } else { 1329 owner = OBJECT(pci_bridge_get_device(bus)); 1330 } 1331 1332 ret = spapr_dt_drc(fdt, offset, owner, 1333 SPAPR_DR_CONNECTOR_TYPE_PCI); 1334 if (ret) { 1335 return ret; 1336 } 1337 1338 return offset; 1339} 1340 1341char *spapr_pci_fw_dev_name(PCIDevice *dev) 1342{ 1343 const gchar *basename; 1344 int slot = PCI_SLOT(dev->devfn); 1345 int func = PCI_FUNC(dev->devfn); 1346 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1347 1348 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, 1349 ccode & 0xff); 1350 1351 if (func != 0) { 1352 return g_strdup_printf("%s@%x,%x", basename, slot, func); 1353 } else { 1354 return g_strdup_printf("%s@%x", basename, slot); 1355 } 1356} 1357 1358/* create OF node for pci device and required OF DT properties */ 1359static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1360 void *fdt, int parent_offset) 1361{ 1362 int offset; 1363 g_autofree gchar *nodename = spapr_pci_fw_dev_name(dev); 1364 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1365 ResourceProps rp; 1366 SpaprDrc *drc = drc_from_dev(sphb, dev); 1367 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2); 1368 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2); 1369 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1); 1370 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1371 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1); 1372 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2); 1373 uint32_t subsystem_vendor_id = 1374 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2); 1375 uint32_t cache_line_size = 1376 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1); 1377 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1378 gchar *loc_code; 1379 1380 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename)); 1381 1382 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 1383 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id)); 1384 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id)); 1385 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id)); 1386 1387 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); 1388 if (irq_pin) { 1389 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin)); 1390 } 1391 1392 if (subsystem_id) { 1393 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id)); 1394 } 1395 1396 if (subsystem_vendor_id) { 1397 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 1398 subsystem_vendor_id)); 1399 } 1400 1401 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size)); 1402 1403 1404 /* the following fdt cells are masked off the pci status register */ 1405 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1406 PCI_STATUS_DEVSEL_MASK & pci_status)); 1407 1408 if (pci_status & PCI_STATUS_FAST_BACK) { 1409 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1410 } 1411 if (pci_status & PCI_STATUS_66MHZ) { 1412 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1413 } 1414 if (pci_status & PCI_STATUS_UDF) { 1415 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1416 } 1417 1418 loc_code = spapr_phb_get_loc_code(sphb, dev); 1419 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code)); 1420 g_free(loc_code); 1421 1422 if (drc) { 1423 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", 1424 spapr_drc_index(drc))); 1425 } 1426 1427 if (msi_present(dev)) { 1428 uint32_t max_msi = msi_nr_vectors_allocated(dev); 1429 if (max_msi) { 1430 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1431 } 1432 } 1433 if (msix_present(dev)) { 1434 uint32_t max_msix = dev->msix_entries_nr; 1435 if (max_msix) { 1436 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1437 } 1438 } 1439 1440 populate_resource_props(dev, &rp); 1441 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1442 1443 if (sphb->pcie_ecs && pci_is_express(dev)) { 1444 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); 1445 } 1446 1447 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); 1448 1449 if (!pc->is_bridge) { 1450 /* Properties only for non-bridges */ 1451 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1); 1452 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1); 1453 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant)); 1454 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency)); 1455 return offset; 1456 } else { 1457 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1458 1459 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset); 1460 } 1461} 1462 1463/* Callback to be called during DRC release. */ 1464void spapr_phb_remove_pci_device_cb(DeviceState *dev) 1465{ 1466 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 1467 1468 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 1469 object_unparent(OBJECT(dev)); 1470} 1471 1472int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 1473 void *fdt, int *fdt_start_offset, Error **errp) 1474{ 1475 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); 1476 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); 1477 PCIDevice *pdev = PCI_DEVICE(drc->dev); 1478 1479 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0); 1480 return 0; 1481} 1482 1483static void spapr_pci_bridge_plug(SpaprPhbState *phb, 1484 PCIBridge *bridge) 1485{ 1486 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1487 1488 add_drcs(phb, bus); 1489} 1490 1491/* Returns non-zero if the value of "chassis_nr" is already in use */ 1492static int check_chassis_nr(Object *obj, void *opaque) 1493{ 1494 int new_chassis_nr = 1495 object_property_get_uint(opaque, "chassis_nr", &error_abort); 1496 int chassis_nr = 1497 object_property_get_uint(obj, "chassis_nr", NULL); 1498 1499 if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) { 1500 return 0; 1501 } 1502 1503 /* Skip unsupported bridge types */ 1504 if (!chassis_nr) { 1505 return 0; 1506 } 1507 1508 /* Skip self */ 1509 if (obj == opaque) { 1510 return 0; 1511 } 1512 1513 return chassis_nr == new_chassis_nr; 1514} 1515 1516static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp) 1517{ 1518 int chassis_nr = 1519 object_property_get_uint(bridge, "chassis_nr", NULL); 1520 1521 /* 1522 * slotid_cap_init() already ensures that "chassis_nr" isn't null for 1523 * standard PCI bridges, so this really tells if "chassis_nr" is present 1524 * or not. 1525 */ 1526 if (!chassis_nr) { 1527 error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property"); 1528 error_append_hint(errp, "Try -device pci-bridge instead.\n"); 1529 return false; 1530 } 1531 1532 /* We want unique values for "chassis_nr" */ 1533 if (object_child_foreach_recursive(object_get_root(), check_chassis_nr, 1534 bridge)) { 1535 error_setg(errp, "Bridge chassis %d already in use", chassis_nr); 1536 return false; 1537 } 1538 1539 return true; 1540} 1541 1542static void spapr_pci_pre_plug(HotplugHandler *plug_handler, 1543 DeviceState *plugged_dev, Error **errp) 1544{ 1545 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1546 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1547 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1548 SpaprDrc *drc = drc_from_dev(phb, pdev); 1549 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1550 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1551 1552 if (!phb->dr_enabled) { 1553 /* if this is a hotplug operation initiated by the user 1554 * we need to let them know it's not enabled 1555 */ 1556 if (plugged_dev->hotplugged) { 1557 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1558 object_get_typename(OBJECT(phb))); 1559 return; 1560 } 1561 } 1562 1563 if (pc->is_bridge) { 1564 if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) { 1565 return; 1566 } 1567 } 1568 1569 /* Following the QEMU convention used for PCIe multifunction 1570 * hotplug, we do not allow functions to be hotplugged to a 1571 * slot that already has function 0 present 1572 */ 1573 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && 1574 PCI_FUNC(pdev->devfn) != 0) { 1575 error_setg(errp, "PCI: slot %d function 0 already occupied by %s," 1576 " additional functions can no longer be exposed to guest.", 1577 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); 1578 } 1579 1580 if (drc && drc->dev) { 1581 error_setg(errp, "PCI: slot %d already occupied by %s", slotnr, 1582 pci_get_function_0(PCI_DEVICE(drc->dev))->name); 1583 return; 1584 } 1585} 1586 1587static void spapr_pci_plug(HotplugHandler *plug_handler, 1588 DeviceState *plugged_dev, Error **errp) 1589{ 1590 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1591 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1592 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1593 SpaprDrc *drc = drc_from_dev(phb, pdev); 1594 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1595 1596 /* 1597 * If DR is disabled we don't need to do anything in the case of 1598 * hotplug or coldplug callbacks. 1599 */ 1600 if (!phb->dr_enabled) { 1601 return; 1602 } 1603 1604 g_assert(drc); 1605 1606 if (pc->is_bridge) { 1607 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev)); 1608 } 1609 1610 /* spapr_pci_pre_plug() already checked the DRC is attachable */ 1611 spapr_drc_attach(drc, DEVICE(pdev)); 1612 1613 /* If this is function 0, signal hotplug for all the device functions. 1614 * Otherwise defer sending the hotplug event. 1615 */ 1616 if (!spapr_drc_hotplugged(plugged_dev)) { 1617 spapr_drc_reset(drc); 1618 } else if (PCI_FUNC(pdev->devfn) == 0) { 1619 int i; 1620 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev)); 1621 1622 for (i = 0; i < 8; i++) { 1623 SpaprDrc *func_drc; 1624 SpaprDrcClass *func_drck; 1625 SpaprDREntitySense state; 1626 1627 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1628 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1629 state = func_drck->dr_entity_sense(func_drc); 1630 1631 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1632 spapr_hotplug_req_add_by_index(func_drc); 1633 } 1634 } 1635 } 1636} 1637 1638static void spapr_pci_bridge_unplug(SpaprPhbState *phb, 1639 PCIBridge *bridge) 1640{ 1641 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1642 1643 remove_drcs(phb, bus); 1644} 1645 1646static void spapr_pci_unplug(HotplugHandler *plug_handler, 1647 DeviceState *plugged_dev, Error **errp) 1648{ 1649 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1650 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1651 1652 /* some version guests do not wait for completion of a device 1653 * cleanup (generally done asynchronously by the kernel) before 1654 * signaling to QEMU that the device is safe, but instead sleep 1655 * for some 'safe' period of time. unfortunately on a busy host 1656 * this sleep isn't guaranteed to be long enough, resulting in 1657 * bad things like IRQ lines being left asserted during final 1658 * device removal. to deal with this we call reset just prior 1659 * to finalizing the device, which will put the device back into 1660 * an 'idle' state, as the device cleanup code expects. 1661 */ 1662 pci_device_reset(PCI_DEVICE(plugged_dev)); 1663 1664 if (pc->is_bridge) { 1665 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev)); 1666 return; 1667 } 1668 1669 qdev_unrealize(plugged_dev); 1670} 1671 1672static void spapr_pci_unplug_request(HotplugHandler *plug_handler, 1673 DeviceState *plugged_dev, Error **errp) 1674{ 1675 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1676 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1677 SpaprDrc *drc = drc_from_dev(phb, pdev); 1678 1679 if (!phb->dr_enabled) { 1680 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1681 object_get_typename(OBJECT(phb))); 1682 return; 1683 } 1684 1685 g_assert(drc); 1686 g_assert(drc->dev == plugged_dev); 1687 1688 if (!spapr_drc_unplug_requested(drc)) { 1689 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1690 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1691 SpaprDrc *func_drc; 1692 SpaprDrcClass *func_drck; 1693 SpaprDREntitySense state; 1694 int i; 1695 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev)); 1696 1697 if (pc->is_bridge) { 1698 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported"); 1699 return; 1700 } 1701 if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) { 1702 error_setg(errp, "PCI: Cannot unplug NVLink2 devices"); 1703 return; 1704 } 1705 1706 /* ensure any other present functions are pending unplug */ 1707 if (PCI_FUNC(pdev->devfn) == 0) { 1708 for (i = 1; i < 8; i++) { 1709 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1710 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1711 state = func_drck->dr_entity_sense(func_drc); 1712 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT 1713 && !spapr_drc_unplug_requested(func_drc)) { 1714 /* 1715 * Attempting to remove function 0 of a multifunction 1716 * device will will cascade into removing all child 1717 * functions, even if their unplug weren't requested 1718 * beforehand. 1719 */ 1720 spapr_drc_unplug_request(func_drc); 1721 } 1722 } 1723 } 1724 1725 spapr_drc_unplug_request(drc); 1726 1727 /* if this isn't func 0, defer unplug event. otherwise signal removal 1728 * for all present functions 1729 */ 1730 if (PCI_FUNC(pdev->devfn) == 0) { 1731 for (i = 7; i >= 0; i--) { 1732 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1733 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1734 state = func_drck->dr_entity_sense(func_drc); 1735 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1736 spapr_hotplug_req_remove_by_index(func_drc); 1737 } 1738 } 1739 } 1740 } else { 1741 error_setg(errp, 1742 "PCI device unplug already in progress for device %s", 1743 drc->dev->id); 1744 } 1745} 1746 1747static void spapr_phb_finalizefn(Object *obj) 1748{ 1749 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); 1750 1751 g_free(sphb->dtbusname); 1752 sphb->dtbusname = NULL; 1753} 1754 1755static void spapr_phb_unrealize(DeviceState *dev) 1756{ 1757 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1758 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1759 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1760 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); 1761 SpaprTceTable *tcet; 1762 int i; 1763 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1764 1765 spapr_phb_nvgpu_free(sphb); 1766 1767 if (sphb->msi) { 1768 g_hash_table_unref(sphb->msi); 1769 sphb->msi = NULL; 1770 } 1771 1772 /* 1773 * Remove IO/MMIO subregions and aliases, rest should get cleaned 1774 * via PHB's unrealize->object_finalize 1775 */ 1776 for (i = windows_supported - 1; i >= 0; i--) { 1777 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 1778 if (tcet) { 1779 memory_region_del_subregion(&sphb->iommu_root, 1780 spapr_tce_get_iommu(tcet)); 1781 } 1782 } 1783 1784 remove_drcs(sphb, phb->bus); 1785 1786 for (i = PCI_NUM_PINS - 1; i >= 0; i--) { 1787 if (sphb->lsi_table[i].irq) { 1788 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); 1789 sphb->lsi_table[i].irq = 0; 1790 } 1791 } 1792 1793 QLIST_REMOVE(sphb, list); 1794 1795 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); 1796 1797 /* 1798 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have 1799 * unmapped all sections. Remove the listeners now, before destroying the 1800 * address space. 1801 */ 1802 address_space_remove_listeners(&sphb->iommu_as); 1803 address_space_destroy(&sphb->iommu_as); 1804 1805 qbus_set_hotplug_handler(BUS(phb->bus), NULL); 1806 pci_unregister_root_bus(phb->bus); 1807 1808 memory_region_del_subregion(get_system_memory(), &sphb->iowindow); 1809 if (sphb->mem64_win_pciaddr != (hwaddr)-1) { 1810 memory_region_del_subregion(get_system_memory(), &sphb->mem64window); 1811 } 1812 memory_region_del_subregion(get_system_memory(), &sphb->mem32window); 1813} 1814 1815static void spapr_phb_destroy_msi(gpointer opaque) 1816{ 1817 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1818 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 1819 SpaprPciMsi *msi = opaque; 1820 1821 if (!smc->legacy_irq_allocation) { 1822 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 1823 } 1824 spapr_irq_free(spapr, msi->first_irq, msi->num); 1825 g_free(msi); 1826} 1827 1828static void spapr_phb_realize(DeviceState *dev, Error **errp) 1829{ 1830 ERRP_GUARD(); 1831 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 1832 * tries to add a sPAPR PHB to a non-pseries machine. 1833 */ 1834 SpaprMachineState *spapr = 1835 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 1836 TYPE_SPAPR_MACHINE); 1837 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; 1838 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1839 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1840 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1841 MachineState *ms = MACHINE(spapr); 1842 char *namebuf; 1843 int i; 1844 PCIBus *bus; 1845 uint64_t msi_window_size = 4096; 1846 SpaprTceTable *tcet; 1847 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1848 1849 if (!spapr) { 1850 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); 1851 return; 1852 } 1853 1854 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ 1855 1856 if (sphb->mem64_win_size != 0) { 1857 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1858 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx 1859 " (max 2 GiB)", sphb->mem_win_size); 1860 return; 1861 } 1862 1863 /* 64-bit window defaults to identity mapping */ 1864 sphb->mem64_win_pciaddr = sphb->mem64_win_addr; 1865 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1866 /* 1867 * For compatibility with old configuration, if no 64-bit MMIO 1868 * window is specified, but the ordinary (32-bit) memory 1869 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit 1870 * window, with a 64-bit MMIO window following on immediately 1871 * afterwards 1872 */ 1873 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; 1874 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; 1875 sphb->mem64_win_pciaddr = 1876 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; 1877 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; 1878 } 1879 1880 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1881 SpaprPhbState *s; 1882 1883 error_setg(errp, "PCI host bridges must have unique indexes"); 1884 error_append_hint(errp, "The following indexes are already in use:"); 1885 QLIST_FOREACH(s, &spapr->phbs, list) { 1886 error_append_hint(errp, " %d", s->index); 1887 } 1888 error_append_hint(errp, "\nTry another value for the index property\n"); 1889 return; 1890 } 1891 1892 if (sphb->numa_node != -1 && 1893 (sphb->numa_node >= MAX_NODES || 1894 !ms->numa_state->nodes[sphb->numa_node].present)) { 1895 error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); 1896 return; 1897 } 1898 1899 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1900 1901 /* Initialize memory regions */ 1902 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); 1903 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1904 g_free(namebuf); 1905 1906 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); 1907 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), 1908 namebuf, &sphb->memspace, 1909 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1910 g_free(namebuf); 1911 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1912 &sphb->mem32window); 1913 1914 if (sphb->mem64_win_size != 0) { 1915 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); 1916 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), 1917 namebuf, &sphb->memspace, 1918 sphb->mem64_win_pciaddr, sphb->mem64_win_size); 1919 g_free(namebuf); 1920 1921 memory_region_add_subregion(get_system_memory(), 1922 sphb->mem64_win_addr, 1923 &sphb->mem64window); 1924 } 1925 1926 /* Initialize IO regions */ 1927 namebuf = g_strdup_printf("%s.io", sphb->dtbusname); 1928 memory_region_init(&sphb->iospace, OBJECT(sphb), 1929 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1930 g_free(namebuf); 1931 1932 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); 1933 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1934 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1935 g_free(namebuf); 1936 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1937 &sphb->iowindow); 1938 1939 bus = pci_register_root_bus(dev, NULL, 1940 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, 1941 &sphb->memspace, &sphb->iospace, 1942 PCI_DEVFN(0, 0), PCI_NUM_PINS, 1943 TYPE_PCI_BUS); 1944 1945 /* 1946 * Despite resembling a vanilla PCI bus in most ways, the PAPR 1947 * para-virtualized PCI bus *does* permit PCI-E extended config 1948 * space access 1949 */ 1950 if (sphb->pcie_ecs) { 1951 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 1952 } 1953 phb->bus = bus; 1954 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb)); 1955 1956 /* 1957 * Initialize PHB address space. 1958 * By default there will be at least one subregion for default 1959 * 32bit DMA window. 1960 * Later the guest might want to create another DMA window 1961 * which will become another memory subregion. 1962 */ 1963 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); 1964 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1965 namebuf, UINT64_MAX); 1966 g_free(namebuf); 1967 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1968 sphb->dtbusname); 1969 1970 /* 1971 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1972 * we need to allocate some memory to catch those writes coming 1973 * from msi_notify()/msix_notify(). 1974 * As MSIMessage:addr is going to be the same and MSIMessage:data 1975 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1976 * be used. 1977 * 1978 * For KVM we want to ensure that this memory is a full page so that 1979 * our memory slot is of page size granularity. 1980 */ 1981 if (kvm_enabled()) { 1982 msi_window_size = qemu_real_host_page_size; 1983 } 1984 1985 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, 1986 "msi", msi_window_size); 1987 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1988 &sphb->msiwindow); 1989 1990 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1991 1992 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1993 1994 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1995 1996 /* Initialize the LSI table */ 1997 for (i = 0; i < PCI_NUM_PINS; i++) { 1998 int irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; 1999 2000 if (smc->legacy_irq_allocation) { 2001 irq = spapr_irq_findone(spapr, errp); 2002 if (irq < 0) { 2003 error_prepend(errp, "can't allocate LSIs: "); 2004 /* 2005 * Older machines will never support PHB hotplug, ie, this is an 2006 * init only path and QEMU will terminate. No need to rollback. 2007 */ 2008 return; 2009 } 2010 } 2011 2012 if (spapr_irq_claim(spapr, irq, true, errp) < 0) { 2013 error_prepend(errp, "can't allocate LSIs: "); 2014 goto unrealize; 2015 } 2016 2017 sphb->lsi_table[i].irq = irq; 2018 } 2019 2020 /* allocate connectors for child PCI devices */ 2021 add_drcs(sphb, phb->bus); 2022 2023 /* DMA setup */ 2024 for (i = 0; i < windows_supported; ++i) { 2025 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); 2026 if (!tcet) { 2027 error_setg(errp, "Creating window#%d failed for %s", 2028 i, sphb->dtbusname); 2029 goto unrealize; 2030 } 2031 memory_region_add_subregion(&sphb->iommu_root, 0, 2032 spapr_tce_get_iommu(tcet)); 2033 } 2034 2035 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, 2036 spapr_phb_destroy_msi); 2037 return; 2038 2039unrealize: 2040 spapr_phb_unrealize(dev); 2041} 2042 2043static int spapr_phb_children_reset(Object *child, void *opaque) 2044{ 2045 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 2046 2047 if (dev) { 2048 device_legacy_reset(dev); 2049 } 2050 2051 return 0; 2052} 2053 2054void spapr_phb_dma_reset(SpaprPhbState *sphb) 2055{ 2056 int i; 2057 SpaprTceTable *tcet; 2058 2059 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { 2060 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 2061 2062 if (tcet && tcet->nb_table) { 2063 spapr_tce_table_disable(tcet); 2064 } 2065 } 2066 2067 /* Register default 32bit DMA window */ 2068 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); 2069 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, 2070 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); 2071} 2072 2073static void spapr_phb_reset(DeviceState *qdev) 2074{ 2075 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); 2076 Error *err = NULL; 2077 2078 spapr_phb_dma_reset(sphb); 2079 spapr_phb_nvgpu_free(sphb); 2080 spapr_phb_nvgpu_setup(sphb, &err); 2081 if (err) { 2082 error_report_err(err); 2083 } 2084 2085 /* Reset the IOMMU state */ 2086 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 2087 2088 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { 2089 spapr_phb_vfio_reset(qdev); 2090 } 2091 2092 g_hash_table_remove_all(sphb->msi); 2093} 2094 2095static Property spapr_phb_properties[] = { 2096 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), 2097 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, 2098 SPAPR_PCI_MEM32_WIN_SIZE), 2099 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, 2100 SPAPR_PCI_MEM64_WIN_SIZE), 2101 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, 2102 SPAPR_PCI_IO_WIN_SIZE), 2103 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, 2104 true), 2105 /* Default DMA window is 0..1GB */ 2106 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), 2107 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), 2108 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, 2109 0x800000000000000ULL), 2110 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), 2111 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, 2112 (1ULL << 12) | (1ULL << 16) 2113 | (1ULL << 21) | (1ULL << 24)), 2114 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), 2115 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, 2116 pre_2_8_migration, false), 2117 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, 2118 pcie_ecs, true), 2119 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0), 2120 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0), 2121 DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState, 2122 pre_5_1_assoc, false), 2123 DEFINE_PROP_END_OF_LIST(), 2124}; 2125 2126static const VMStateDescription vmstate_spapr_pci_lsi = { 2127 .name = "spapr_pci/lsi", 2128 .version_id = 1, 2129 .minimum_version_id = 1, 2130 .fields = (VMStateField[]) { 2131 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL), 2132 2133 VMSTATE_END_OF_LIST() 2134 }, 2135}; 2136 2137static const VMStateDescription vmstate_spapr_pci_msi = { 2138 .name = "spapr_pci/msi", 2139 .version_id = 1, 2140 .minimum_version_id = 1, 2141 .fields = (VMStateField []) { 2142 VMSTATE_UINT32(key, SpaprPciMsiMig), 2143 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig), 2144 VMSTATE_UINT32(value.num, SpaprPciMsiMig), 2145 VMSTATE_END_OF_LIST() 2146 }, 2147}; 2148 2149static int spapr_pci_pre_save(void *opaque) 2150{ 2151 SpaprPhbState *sphb = opaque; 2152 GHashTableIter iter; 2153 gpointer key, value; 2154 int i; 2155 2156 if (sphb->pre_2_8_migration) { 2157 sphb->mig_liobn = sphb->dma_liobn[0]; 2158 sphb->mig_mem_win_addr = sphb->mem_win_addr; 2159 sphb->mig_mem_win_size = sphb->mem_win_size; 2160 sphb->mig_io_win_addr = sphb->io_win_addr; 2161 sphb->mig_io_win_size = sphb->io_win_size; 2162 2163 if ((sphb->mem64_win_size != 0) 2164 && (sphb->mem64_win_addr 2165 == (sphb->mem_win_addr + sphb->mem_win_size))) { 2166 sphb->mig_mem_win_size += sphb->mem64_win_size; 2167 } 2168 } 2169 2170 g_free(sphb->msi_devs); 2171 sphb->msi_devs = NULL; 2172 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 2173 if (!sphb->msi_devs_num) { 2174 return 0; 2175 } 2176 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num); 2177 2178 g_hash_table_iter_init(&iter, sphb->msi); 2179 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 2180 sphb->msi_devs[i].key = *(uint32_t *) key; 2181 sphb->msi_devs[i].value = *(SpaprPciMsi *) value; 2182 } 2183 2184 return 0; 2185} 2186 2187static int spapr_pci_post_save(void *opaque) 2188{ 2189 SpaprPhbState *sphb = opaque; 2190 2191 g_free(sphb->msi_devs); 2192 sphb->msi_devs = NULL; 2193 sphb->msi_devs_num = 0; 2194 return 0; 2195} 2196 2197static int spapr_pci_post_load(void *opaque, int version_id) 2198{ 2199 SpaprPhbState *sphb = opaque; 2200 gpointer key, value; 2201 int i; 2202 2203 for (i = 0; i < sphb->msi_devs_num; ++i) { 2204 key = g_memdup(&sphb->msi_devs[i].key, 2205 sizeof(sphb->msi_devs[i].key)); 2206 value = g_memdup(&sphb->msi_devs[i].value, 2207 sizeof(sphb->msi_devs[i].value)); 2208 g_hash_table_insert(sphb->msi, key, value); 2209 } 2210 g_free(sphb->msi_devs); 2211 sphb->msi_devs = NULL; 2212 sphb->msi_devs_num = 0; 2213 2214 return 0; 2215} 2216 2217static bool pre_2_8_migration(void *opaque, int version_id) 2218{ 2219 SpaprPhbState *sphb = opaque; 2220 2221 return sphb->pre_2_8_migration; 2222} 2223 2224static const VMStateDescription vmstate_spapr_pci = { 2225 .name = "spapr_pci", 2226 .version_id = 2, 2227 .minimum_version_id = 2, 2228 .pre_save = spapr_pci_pre_save, 2229 .post_save = spapr_pci_post_save, 2230 .post_load = spapr_pci_post_load, 2231 .fields = (VMStateField[]) { 2232 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), 2233 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), 2234 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), 2235 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), 2236 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), 2237 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), 2238 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, 2239 vmstate_spapr_pci_lsi, SpaprPciLsi), 2240 VMSTATE_INT32(msi_devs_num, SpaprPhbState), 2241 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, 2242 vmstate_spapr_pci_msi, SpaprPciMsiMig), 2243 VMSTATE_END_OF_LIST() 2244 }, 2245}; 2246 2247static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 2248 PCIBus *rootbus) 2249{ 2250 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 2251 2252 return sphb->dtbusname; 2253} 2254 2255static void spapr_phb_class_init(ObjectClass *klass, void *data) 2256{ 2257 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 2258 DeviceClass *dc = DEVICE_CLASS(klass); 2259 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 2260 2261 hc->root_bus_path = spapr_phb_root_bus_path; 2262 dc->realize = spapr_phb_realize; 2263 dc->unrealize = spapr_phb_unrealize; 2264 device_class_set_props(dc, spapr_phb_properties); 2265 dc->reset = spapr_phb_reset; 2266 dc->vmsd = &vmstate_spapr_pci; 2267 /* Supported by TYPE_SPAPR_MACHINE */ 2268 dc->user_creatable = true; 2269 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 2270 hp->pre_plug = spapr_pci_pre_plug; 2271 hp->plug = spapr_pci_plug; 2272 hp->unplug = spapr_pci_unplug; 2273 hp->unplug_request = spapr_pci_unplug_request; 2274} 2275 2276static const TypeInfo spapr_phb_info = { 2277 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 2278 .parent = TYPE_PCI_HOST_BRIDGE, 2279 .instance_size = sizeof(SpaprPhbState), 2280 .instance_finalize = spapr_phb_finalizefn, 2281 .class_init = spapr_phb_class_init, 2282 .interfaces = (InterfaceInfo[]) { 2283 { TYPE_HOTPLUG_HANDLER }, 2284 { } 2285 } 2286}; 2287 2288static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 2289 void *opaque) 2290{ 2291 unsigned int *bus_no = opaque; 2292 PCIBus *sec_bus = NULL; 2293 2294 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2295 PCI_HEADER_TYPE_BRIDGE)) { 2296 return; 2297 } 2298 2299 (*bus_no)++; 2300 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); 2301 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 2302 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2303 2304 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2305 if (!sec_bus) { 2306 return; 2307 } 2308 2309 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 2310 spapr_phb_pci_enumerate_bridge, bus_no); 2311 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2312} 2313 2314static void spapr_phb_pci_enumerate(SpaprPhbState *phb) 2315{ 2316 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2317 unsigned int bus_no = 0; 2318 2319 pci_for_each_device(bus, pci_bus_num(bus), 2320 spapr_phb_pci_enumerate_bridge, 2321 &bus_no); 2322 2323} 2324 2325int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb, 2326 uint32_t intc_phandle, void *fdt, int *node_offset) 2327{ 2328 int bus_off, i, j, ret; 2329 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 2330 struct { 2331 uint32_t hi; 2332 uint64_t child; 2333 uint64_t parent; 2334 uint64_t size; 2335 } QEMU_PACKED ranges[] = { 2336 { 2337 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 2338 cpu_to_be64(phb->io_win_addr), 2339 cpu_to_be64(memory_region_size(&phb->iospace)), 2340 }, 2341 { 2342 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 2343 cpu_to_be64(phb->mem_win_addr), 2344 cpu_to_be64(phb->mem_win_size), 2345 }, 2346 { 2347 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), 2348 cpu_to_be64(phb->mem64_win_addr), 2349 cpu_to_be64(phb->mem64_win_size), 2350 }, 2351 }; 2352 const unsigned sizeof_ranges = 2353 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); 2354 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 2355 uint32_t interrupt_map_mask[] = { 2356 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 2357 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 2358 uint32_t ddw_applicable[] = { 2359 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), 2360 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), 2361 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) 2362 }; 2363 uint32_t ddw_extensions[] = { 2364 cpu_to_be32(1), 2365 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) 2366 }; 2367 SpaprTceTable *tcet; 2368 SpaprDrc *drc; 2369 Error *err = NULL; 2370 2371 /* Start populating the FDT */ 2372 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); 2373 if (node_offset) { 2374 *node_offset = bus_off; 2375 } 2376 2377 /* Write PHB properties */ 2378 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 2379 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 2380 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 2381 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 2382 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 2383 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 2384 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 2385 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 2386 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", 2387 spapr_irq_nr_msis(spapr))); 2388 2389 /* Dynamic DMA window */ 2390 if (phb->ddw_enabled) { 2391 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, 2392 sizeof(ddw_applicable))); 2393 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", 2394 &ddw_extensions, sizeof(ddw_extensions))); 2395 } 2396 2397 /* Advertise NUMA via ibm,associativity */ 2398 if (phb->numa_node != -1) { 2399 spapr_numa_write_associativity_dt(spapr, fdt, bus_off, phb->numa_node); 2400 } 2401 2402 /* Build the interrupt-map, this must matches what is done 2403 * in pci_swizzle_map_irq_fn 2404 */ 2405 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 2406 &interrupt_map_mask, sizeof(interrupt_map_mask))); 2407 for (i = 0; i < PCI_SLOT_MAX; i++) { 2408 for (j = 0; j < PCI_NUM_PINS; j++) { 2409 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 2410 int lsi_num = pci_swizzle(i, j); 2411 2412 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 2413 irqmap[1] = 0; 2414 irqmap[2] = 0; 2415 irqmap[3] = cpu_to_be32(j+1); 2416 irqmap[4] = cpu_to_be32(intc_phandle); 2417 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); 2418 } 2419 } 2420 /* Write interrupt map */ 2421 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 2422 sizeof(interrupt_map))); 2423 2424 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); 2425 if (!tcet) { 2426 return -1; 2427 } 2428 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 2429 tcet->liobn, tcet->bus_offset, 2430 tcet->nb_table << tcet->page_shift); 2431 2432 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); 2433 if (drc) { 2434 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); 2435 2436 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, 2437 sizeof(drc_index))); 2438 } 2439 2440 /* Walk the bridges and program the bus numbers*/ 2441 spapr_phb_pci_enumerate(phb); 2442 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 2443 2444 /* Walk the bridge and subordinate buses */ 2445 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off); 2446 if (ret < 0) { 2447 return ret; 2448 } 2449 2450 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &err); 2451 if (err) { 2452 error_report_err(err); 2453 } 2454 spapr_phb_nvgpu_ram_populate_dt(phb, fdt); 2455 2456 return 0; 2457} 2458 2459void spapr_pci_rtas_init(void) 2460{ 2461 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 2462 rtas_read_pci_config); 2463 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 2464 rtas_write_pci_config); 2465 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 2466 rtas_ibm_read_pci_config); 2467 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 2468 rtas_ibm_write_pci_config); 2469 if (msi_nonbroken) { 2470 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 2471 "ibm,query-interrupt-source-number", 2472 rtas_ibm_query_interrupt_source_number); 2473 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 2474 rtas_ibm_change_msi); 2475 } 2476 2477 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 2478 "ibm,set-eeh-option", 2479 rtas_ibm_set_eeh_option); 2480 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 2481 "ibm,get-config-addr-info2", 2482 rtas_ibm_get_config_addr_info2); 2483 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 2484 "ibm,read-slot-reset-state2", 2485 rtas_ibm_read_slot_reset_state2); 2486 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 2487 "ibm,set-slot-reset", 2488 rtas_ibm_set_slot_reset); 2489 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 2490 "ibm,configure-pe", 2491 rtas_ibm_configure_pe); 2492 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 2493 "ibm,slot-error-detail", 2494 rtas_ibm_slot_error_detail); 2495} 2496 2497static void spapr_pci_register_types(void) 2498{ 2499 type_register_static(&spapr_phb_info); 2500} 2501 2502type_init(spapr_pci_register_types) 2503 2504static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 2505{ 2506 bool be = *(bool *)opaque; 2507 2508 if (object_dynamic_cast(OBJECT(dev), "VGA") 2509 || object_dynamic_cast(OBJECT(dev), "secondary-vga") 2510 || object_dynamic_cast(OBJECT(dev), "bochs-display") 2511 || object_dynamic_cast(OBJECT(dev), "virtio-vga")) { 2512 object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be, 2513 &error_abort); 2514 } 2515 return 0; 2516} 2517 2518void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian) 2519{ 2520 SpaprPhbState *sphb; 2521 2522 /* 2523 * For backward compatibility with existing guests, we switch 2524 * the endianness of the VGA controller when changing the guest 2525 * interrupt mode 2526 */ 2527 QLIST_FOREACH(sphb, &spapr->phbs, list) { 2528 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 2529 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 2530 &big_endian); 2531 } 2532}