cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

meson.build (680B)

      1riscv_ss = ss.source_set()
      2riscv_ss.add(files('boot.c'), fdt)
      3riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
      4riscv_ss.add(files('riscv_hart.c'))
      5riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
      6riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
      7riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
      8riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
      9riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
     10riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
     11riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
     12
     13hw_arch += {'riscv': riscv_ss}