opentitan.c (11788B)
1/* 2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform 3 * 4 * Copyright (c) 2020 Western Digital 5 * 6 * Provides a board compatible with the OpenTitan FPGA platform: 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#include "qemu/osdep.h" 22#include "hw/riscv/opentitan.h" 23#include "qapi/error.h" 24#include "hw/boards.h" 25#include "hw/misc/unimp.h" 26#include "hw/riscv/boot.h" 27#include "qemu/units.h" 28#include "sysemu/sysemu.h" 29 30static const MemMapEntry ibex_memmap[] = { 31 [IBEX_DEV_ROM] = { 0x00008000, 16 * KiB }, 32 [IBEX_DEV_RAM] = { 0x10000000, 0x10000 }, 33 [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 }, 34 [IBEX_DEV_UART] = { 0x40000000, 0x1000 }, 35 [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 }, 36 [IBEX_DEV_SPI] = { 0x40050000, 0x1000 }, 37 [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, 38 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, 39 [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 }, 40 [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 }, 41 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, 42 [IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 }, 43 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, 44 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 }, 45 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 }, 46 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, 47 [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 }, 48 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 }, 49 [IBEX_DEV_PLIC] = { 0x41010000, 0x1000 }, 50 [IBEX_DEV_AES] = { 0x41100000, 0x1000 }, 51 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, 52 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, 53 [IBEX_DEV_KEYMGR] = { 0x41130000, 0x1000 }, 54 [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 }, 55 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 }, 56 [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 }, 57 [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 }, 58 [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 }, 59 [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, 60 [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 }, 61 [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 }, 62 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, 63}; 64 65static void opentitan_board_init(MachineState *machine) 66{ 67 const MemMapEntry *memmap = ibex_memmap; 68 OpenTitanState *s = g_new0(OpenTitanState, 1); 69 MemoryRegion *sys_mem = get_system_memory(); 70 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 71 72 /* Initialize SoC */ 73 object_initialize_child(OBJECT(machine), "soc", &s->soc, 74 TYPE_RISCV_IBEX_SOC); 75 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 76 77 memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram", 78 memmap[IBEX_DEV_RAM].size, &error_fatal); 79 memory_region_add_subregion(sys_mem, 80 memmap[IBEX_DEV_RAM].base, main_mem); 81 82 if (machine->firmware) { 83 riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL); 84 } 85 86 if (machine->kernel_filename) { 87 riscv_load_kernel(machine->kernel_filename, 88 memmap[IBEX_DEV_RAM].base, NULL); 89 } 90} 91 92static void opentitan_machine_init(MachineClass *mc) 93{ 94 mc->desc = "RISC-V Board compatible with OpenTitan"; 95 mc->init = opentitan_board_init; 96 mc->max_cpus = 1; 97 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX; 98} 99 100DEFINE_MACHINE("opentitan", opentitan_machine_init) 101 102static void lowrisc_ibex_soc_init(Object *obj) 103{ 104 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); 105 106 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 107 108 object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC); 109 110 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); 111 112 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); 113} 114 115static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 116{ 117 const MemMapEntry *memmap = ibex_memmap; 118 MachineState *ms = MACHINE(qdev_get_machine()); 119 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc); 120 MemoryRegion *sys_mem = get_system_memory(); 121 int i; 122 123 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 124 &error_abort); 125 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 126 &error_abort); 127 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort); 128 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 129 130 /* Boot ROM */ 131 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom", 132 memmap[IBEX_DEV_ROM].size, &error_fatal); 133 memory_region_add_subregion(sys_mem, 134 memmap[IBEX_DEV_ROM].base, &s->rom); 135 136 /* Flash memory */ 137 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash", 138 memmap[IBEX_DEV_FLASH].size, &error_fatal); 139 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), 140 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0, 141 memmap[IBEX_DEV_FLASH_VIRTUAL].size); 142 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, 143 &s->flash_mem); 144 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base, 145 &s->flash_alias); 146 147 /* PLIC */ 148 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) { 149 return; 150 } 151 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base); 152 153 for (i = 0; i < ms->smp.cpus; i++) { 154 CPUState *cpu = qemu_get_cpu(i); 155 156 qdev_connect_gpio_out(DEVICE(&s->plic), i, 157 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT)); 158 } 159 160 /* UART */ 161 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0)); 162 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) { 163 return; 164 } 165 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); 166 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 167 0, qdev_get_gpio_in(DEVICE(&s->plic), 168 IBEX_UART0_TX_WATERMARK_IRQ)); 169 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 170 1, qdev_get_gpio_in(DEVICE(&s->plic), 171 IBEX_UART0_RX_WATERMARK_IRQ)); 172 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 173 2, qdev_get_gpio_in(DEVICE(&s->plic), 174 IBEX_UART0_TX_EMPTY_IRQ)); 175 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 176 3, qdev_get_gpio_in(DEVICE(&s->plic), 177 IBEX_UART0_RX_OVERFLOW_IRQ)); 178 179 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) { 180 return; 181 } 182 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base); 183 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 184 0, qdev_get_gpio_in(DEVICE(&s->plic), 185 IBEX_TIMER_TIMEREXPIRED0_0)); 186 qdev_connect_gpio_out(DEVICE(&s->timer), 0, 187 qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), 188 IRQ_M_TIMER)); 189 190 create_unimplemented_device("riscv.lowrisc.ibex.gpio", 191 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); 192 create_unimplemented_device("riscv.lowrisc.ibex.spi", 193 memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size); 194 create_unimplemented_device("riscv.lowrisc.ibex.i2c", 195 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); 196 create_unimplemented_device("riscv.lowrisc.ibex.pattgen", 197 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size); 198 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl", 199 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size); 200 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl", 201 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size); 202 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr", 203 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size); 204 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr", 205 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size); 206 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr", 207 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size); 208 create_unimplemented_device("riscv.lowrisc.ibex.pinmux", 209 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size); 210 create_unimplemented_device("riscv.lowrisc.ibex.padctrl", 211 memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size); 212 create_unimplemented_device("riscv.lowrisc.ibex.usbdev", 213 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size); 214 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl", 215 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size); 216 create_unimplemented_device("riscv.lowrisc.ibex.aes", 217 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size); 218 create_unimplemented_device("riscv.lowrisc.ibex.hmac", 219 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size); 220 create_unimplemented_device("riscv.lowrisc.ibex.kmac", 221 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size); 222 create_unimplemented_device("riscv.lowrisc.ibex.keymgr", 223 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size); 224 create_unimplemented_device("riscv.lowrisc.ibex.csrng", 225 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size); 226 create_unimplemented_device("riscv.lowrisc.ibex.entropy", 227 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size); 228 create_unimplemented_device("riscv.lowrisc.ibex.edn0", 229 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size); 230 create_unimplemented_device("riscv.lowrisc.ibex.edn1", 231 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); 232 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", 233 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); 234 create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", 235 memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); 236 create_unimplemented_device("riscv.lowrisc.ibex.otbn", 237 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); 238 create_unimplemented_device("riscv.lowrisc.ibex.peri", 239 memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); 240} 241 242static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) 243{ 244 DeviceClass *dc = DEVICE_CLASS(oc); 245 246 dc->realize = lowrisc_ibex_soc_realize; 247 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 248 dc->user_creatable = false; 249} 250 251static const TypeInfo lowrisc_ibex_soc_type_info = { 252 .name = TYPE_RISCV_IBEX_SOC, 253 .parent = TYPE_DEVICE, 254 .instance_size = sizeof(LowRISCIbexSoCState), 255 .instance_init = lowrisc_ibex_soc_init, 256 .class_init = lowrisc_ibex_soc_class_init, 257}; 258 259static void lowrisc_ibex_soc_register_types(void) 260{ 261 type_register_static(&lowrisc_ibex_soc_type_info); 262} 263 264type_init(lowrisc_ibex_soc_register_types)