sifive_e.c (10658B)
1/* 2 * QEMU RISC-V Board Compatible with SiFive Freedom E SDK 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * Provides a board compatible with the SiFive Freedom E SDK: 7 * 8 * 0) UART 9 * 1) CLINT (Core Level Interruptor) 10 * 2) PLIC (Platform Level Interrupt Controller) 11 * 3) PRCI (Power, Reset, Clock, Interrupt) 12 * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM 13 * 5) Flash memory emulated as RAM 14 * 15 * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. 16 * The OTP ROM and Flash boot code will be emulated in a future version. 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2 or later, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31#include "qemu/osdep.h" 32#include "qemu/error-report.h" 33#include "qapi/error.h" 34#include "hw/boards.h" 35#include "hw/loader.h" 36#include "hw/sysbus.h" 37#include "hw/char/serial.h" 38#include "hw/misc/unimp.h" 39#include "target/riscv/cpu.h" 40#include "hw/riscv/riscv_hart.h" 41#include "hw/riscv/sifive_e.h" 42#include "hw/riscv/boot.h" 43#include "hw/char/sifive_uart.h" 44#include "hw/intc/riscv_aclint.h" 45#include "hw/intc/sifive_plic.h" 46#include "hw/misc/sifive_e_prci.h" 47#include "chardev/char.h" 48#include "sysemu/sysemu.h" 49 50static const MemMapEntry sifive_e_memmap[] = { 51 [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 }, 52 [SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 }, 53 [SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 }, 54 [SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 }, 55 [SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 }, 56 [SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 }, 57 [SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 }, 58 [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 }, 59 [SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 }, 60 [SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 }, 61 [SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 }, 62 [SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 }, 63 [SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 }, 64 [SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 }, 65 [SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 }, 66 [SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 }, 67 [SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 }, 68 [SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 }, 69 [SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 } 70}; 71 72static void sifive_e_machine_init(MachineState *machine) 73{ 74 const MemMapEntry *memmap = sifive_e_memmap; 75 76 SiFiveEState *s = RISCV_E_MACHINE(machine); 77 MemoryRegion *sys_mem = get_system_memory(); 78 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 79 int i; 80 81 /* Initialize SoC */ 82 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC); 83 qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 84 85 /* Data Tightly Integrated Memory */ 86 memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", 87 memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal); 88 memory_region_add_subregion(sys_mem, 89 memmap[SIFIVE_E_DEV_DTIM].base, main_mem); 90 91 /* Mask ROM reset vector */ 92 uint32_t reset_vec[4]; 93 94 if (s->revb) { 95 reset_vec[1] = 0x200102b7; /* 0x1004: lui t0,0x20010 */ 96 } else { 97 reset_vec[1] = 0x204002b7; /* 0x1004: lui t0,0x20400 */ 98 } 99 reset_vec[2] = 0x00028067; /* 0x1008: jr t0 */ 100 101 reset_vec[0] = reset_vec[3] = 0; 102 103 /* copy in the reset vector in little_endian byte order */ 104 for (i = 0; i < sizeof(reset_vec) >> 2; i++) { 105 reset_vec[i] = cpu_to_le32(reset_vec[i]); 106 } 107 rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), 108 memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); 109 110 if (machine->kernel_filename) { 111 riscv_load_kernel(machine->kernel_filename, 112 memmap[SIFIVE_E_DEV_DTIM].base, NULL); 113 } 114} 115 116static bool sifive_e_machine_get_revb(Object *obj, Error **errp) 117{ 118 SiFiveEState *s = RISCV_E_MACHINE(obj); 119 120 return s->revb; 121} 122 123static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp) 124{ 125 SiFiveEState *s = RISCV_E_MACHINE(obj); 126 127 s->revb = value; 128} 129 130static void sifive_e_machine_instance_init(Object *obj) 131{ 132 SiFiveEState *s = RISCV_E_MACHINE(obj); 133 134 s->revb = false; 135} 136 137static void sifive_e_machine_class_init(ObjectClass *oc, void *data) 138{ 139 MachineClass *mc = MACHINE_CLASS(oc); 140 141 mc->desc = "RISC-V Board compatible with SiFive E SDK"; 142 mc->init = sifive_e_machine_init; 143 mc->max_cpus = 1; 144 mc->default_cpu_type = SIFIVE_E_CPU; 145 146 object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb, 147 sifive_e_machine_set_revb); 148 object_class_property_set_description(oc, "revb", 149 "Set on to tell QEMU that it should model " 150 "the revB HiFive1 board"); 151} 152 153static const TypeInfo sifive_e_machine_typeinfo = { 154 .name = MACHINE_TYPE_NAME("sifive_e"), 155 .parent = TYPE_MACHINE, 156 .class_init = sifive_e_machine_class_init, 157 .instance_init = sifive_e_machine_instance_init, 158 .instance_size = sizeof(SiFiveEState), 159}; 160 161static void sifive_e_machine_init_register_types(void) 162{ 163 type_register_static(&sifive_e_machine_typeinfo); 164} 165 166type_init(sifive_e_machine_init_register_types) 167 168static void sifive_e_soc_init(Object *obj) 169{ 170 MachineState *ms = MACHINE(qdev_get_machine()); 171 SiFiveESoCState *s = RISCV_E_SOC(obj); 172 173 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); 174 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, 175 &error_abort); 176 object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); 177 object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, 178 TYPE_SIFIVE_GPIO); 179} 180 181static void sifive_e_soc_realize(DeviceState *dev, Error **errp) 182{ 183 MachineState *ms = MACHINE(qdev_get_machine()); 184 const MemMapEntry *memmap = sifive_e_memmap; 185 SiFiveESoCState *s = RISCV_E_SOC(dev); 186 MemoryRegion *sys_mem = get_system_memory(); 187 188 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, 189 &error_abort); 190 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); 191 192 /* Mask ROM */ 193 memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", 194 memmap[SIFIVE_E_DEV_MROM].size, &error_fatal); 195 memory_region_add_subregion(sys_mem, 196 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); 197 198 /* MMIO */ 199 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, 200 (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0, 201 SIFIVE_E_PLIC_NUM_SOURCES, 202 SIFIVE_E_PLIC_NUM_PRIORITIES, 203 SIFIVE_E_PLIC_PRIORITY_BASE, 204 SIFIVE_E_PLIC_PENDING_BASE, 205 SIFIVE_E_PLIC_ENABLE_BASE, 206 SIFIVE_E_PLIC_ENABLE_STRIDE, 207 SIFIVE_E_PLIC_CONTEXT_BASE, 208 SIFIVE_E_PLIC_CONTEXT_STRIDE, 209 memmap[SIFIVE_E_DEV_PLIC].size); 210 riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, 211 0, ms->smp.cpus, false); 212 riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base + 213 RISCV_ACLINT_SWI_SIZE, 214 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 215 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 216 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false); 217 create_unimplemented_device("riscv.sifive.e.aon", 218 memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); 219 sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); 220 221 /* GPIO */ 222 223 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { 224 return; 225 } 226 227 /* Map GPIO registers */ 228 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base); 229 230 /* Pass all GPIOs to the SOC layer so they are available to the board */ 231 qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); 232 233 /* Connect GPIO interrupts to the PLIC */ 234 for (int i = 0; i < 32; i++) { 235 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i, 236 qdev_get_gpio_in(DEVICE(s->plic), 237 SIFIVE_E_GPIO0_IRQ0 + i)); 238 } 239 240 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, 241 serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); 242 create_unimplemented_device("riscv.sifive.e.qspi0", 243 memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size); 244 create_unimplemented_device("riscv.sifive.e.pwm0", 245 memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size); 246 sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base, 247 serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); 248 create_unimplemented_device("riscv.sifive.e.qspi1", 249 memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size); 250 create_unimplemented_device("riscv.sifive.e.pwm1", 251 memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size); 252 create_unimplemented_device("riscv.sifive.e.qspi2", 253 memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size); 254 create_unimplemented_device("riscv.sifive.e.pwm2", 255 memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size); 256 257 /* Flash memory */ 258 memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", 259 memmap[SIFIVE_E_DEV_XIP].size, &error_fatal); 260 memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base, 261 &s->xip_mem); 262} 263 264static void sifive_e_soc_class_init(ObjectClass *oc, void *data) 265{ 266 DeviceClass *dc = DEVICE_CLASS(oc); 267 268 dc->realize = sifive_e_soc_realize; 269 /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 270 dc->user_creatable = false; 271} 272 273static const TypeInfo sifive_e_soc_type_info = { 274 .name = TYPE_RISCV_E_SOC, 275 .parent = TYPE_DEVICE, 276 .instance_size = sizeof(SiFiveESoCState), 277 .instance_init = sifive_e_soc_init, 278 .class_init = sifive_e_soc_class_init, 279}; 280 281static void sifive_e_soc_register_types(void) 282{ 283 type_register_static(&sifive_e_soc_type_info); 284} 285 286type_init(sifive_e_soc_register_types)