cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

hcd-xhci-sysbus.c (3706B)

      1/*
      2 * USB xHCI controller for system-bus interface
      3 * Based on hcd-echi-sysbus.c
      4
      5 * SPDX-FileCopyrightText: 2020 Xilinx
      6 * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
      7 *
      8 * SPDX-License-Identifier: GPL-2.0-or-later
      9 */
     10#include "qemu/osdep.h"
     11#include "hw/qdev-properties.h"
     12#include "migration/vmstate.h"
     13#include "trace.h"
     14#include "qapi/error.h"
     15#include "hcd-xhci-sysbus.h"
     16#include "hw/acpi/aml-build.h"
     17#include "hw/irq.h"
     18
     19static bool xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level)
     20{
     21    XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci);
     22
     23    qemu_set_irq(s->irq[n], level);
     24
     25    return false;
     26}
     27
     28void xhci_sysbus_reset(DeviceState *dev)
     29{
     30    XHCISysbusState *s = XHCI_SYSBUS(dev);
     31
     32    device_legacy_reset(DEVICE(&s->xhci));
     33}
     34
     35static void xhci_sysbus_realize(DeviceState *dev, Error **errp)
     36{
     37    XHCISysbusState *s = XHCI_SYSBUS(dev);
     38
     39    object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
     40    if (!qdev_realize(DEVICE(&s->xhci), NULL, errp)) {
     41        return;
     42    }
     43    s->irq = g_new0(qemu_irq, s->xhci.numintrs);
     44    qdev_init_gpio_out_named(dev, s->irq, SYSBUS_DEVICE_GPIO_IRQ,
     45                             s->xhci.numintrs);
     46    if (s->xhci.dma_mr) {
     47        s->xhci.as =  g_malloc0(sizeof(AddressSpace));
     48        address_space_init(s->xhci.as, s->xhci.dma_mr, NULL);
     49    } else {
     50        s->xhci.as = &address_space_memory;
     51    }
     52
     53    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->xhci.mem);
     54}
     55
     56static void xhci_sysbus_instance_init(Object *obj)
     57{
     58    XHCISysbusState *s = XHCI_SYSBUS(obj);
     59
     60    object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
     61    qdev_alias_all_properties(DEVICE(&s->xhci), obj);
     62
     63    object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
     64                             (Object **)&s->xhci.dma_mr,
     65                             qdev_prop_allow_set_link_before_realize,
     66                             OBJ_PROP_LINK_STRONG);
     67    s->xhci.intr_update = NULL;
     68    s->xhci.intr_raise = xhci_sysbus_intr_raise;
     69}
     70
     71void xhci_sysbus_build_aml(Aml *scope, uint32_t mmio, unsigned int irq)
     72{
     73    Aml *dev = aml_device("XHCI");
     74    Aml *crs = aml_resource_template();
     75
     76    aml_append(crs, aml_memory32_fixed(mmio, XHCI_LEN_REGS, AML_READ_WRITE));
     77    aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
     78                                  AML_EXCLUSIVE, &irq, 1));
     79
     80    aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0D10")));
     81    aml_append(dev, aml_name_decl("_CRS", crs));
     82    aml_append(scope, dev);
     83}
     84
     85static Property xhci_sysbus_props[] = {
     86    DEFINE_PROP_UINT32("intrs", XHCISysbusState, xhci.numintrs, XHCI_MAXINTRS),
     87    DEFINE_PROP_UINT32("slots", XHCISysbusState, xhci.numslots, XHCI_MAXSLOTS),
     88    DEFINE_PROP_END_OF_LIST(),
     89};
     90
     91static const VMStateDescription vmstate_xhci_sysbus = {
     92    .name = "xhci-sysbus",
     93    .version_id = 1,
     94    .fields = (VMStateField[]) {
     95        VMSTATE_STRUCT(xhci, XHCISysbusState, 1, vmstate_xhci, XHCIState),
     96        VMSTATE_END_OF_LIST()
     97    }
     98};
     99
    100static void xhci_sysbus_class_init(ObjectClass *klass, void *data)
    101{
    102    DeviceClass *dc = DEVICE_CLASS(klass);
    103
    104    dc->reset = xhci_sysbus_reset;
    105    dc->realize = xhci_sysbus_realize;
    106    dc->vmsd = &vmstate_xhci_sysbus;
    107    device_class_set_props(dc, xhci_sysbus_props);
    108}
    109
    110static const TypeInfo xhci_sysbus_info = {
    111    .name          = TYPE_XHCI_SYSBUS,
    112    .parent        = TYPE_SYS_BUS_DEVICE,
    113    .instance_size = sizeof(XHCISysbusState),
    114    .class_init    = xhci_sysbus_class_init,
    115    .instance_init = xhci_sysbus_instance_init
    116};
    117
    118static void xhci_sysbus_register_types(void)
    119{
    120    type_register_static(&xhci_sysbus_info);
    121}
    122
    123type_init(xhci_sysbus_register_types);