cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

char-serial.h (1684B)


      1/*
      2 * QEMU System Emulator
      3 *
      4 * Copyright (c) 2003-2008 Fabrice Bellard
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24#ifndef CHAR_SERIAL_H
     25#define CHAR_SERIAL_H
     26
     27#include "chardev/char.h"
     28
     29#define CHR_IOCTL_SERIAL_SET_PARAMS   1
     30typedef struct {
     31    int speed;
     32    int parity;
     33    int data_bits;
     34    int stop_bits;
     35} QEMUSerialSetParams;
     36
     37#define CHR_IOCTL_SERIAL_SET_BREAK    2
     38
     39#define CHR_IOCTL_SERIAL_SET_TIOCM   13
     40#define CHR_IOCTL_SERIAL_GET_TIOCM   14
     41
     42#define CHR_TIOCM_CTS   0x020
     43#define CHR_TIOCM_CAR   0x040
     44#define CHR_TIOCM_DSR   0x100
     45#define CHR_TIOCM_RI    0x080
     46#define CHR_TIOCM_DTR   0x002
     47#define CHR_TIOCM_RTS   0x004
     48
     49#endif