cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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translator.h (6346B)

      1/*
      2 * Generic intermediate code generation.
      3 *
      4 * Copyright (C) 2016-2017 Lluís Vilanova <vilanova@ac.upc.edu>
      5 *
      6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
      7 * See the COPYING file in the top-level directory.
      8 */
      9
     10#ifndef EXEC__TRANSLATOR_H
     11#define EXEC__TRANSLATOR_H
     12
     13/*
     14 * Include this header from a target-specific file, and add a
     15 *
     16 *     DisasContextBase base;
     17 *
     18 * member in your target-specific DisasContext.
     19 */
     20
     21
     22#include "qemu/bswap.h"
     23#include "exec/exec-all.h"
     24#include "exec/cpu_ldst.h"
     25#include "exec/plugin-gen.h"
     26#include "exec/translate-all.h"
     27#include "tcg/tcg.h"
     28
     29
     30/**
     31 * DisasJumpType:
     32 * @DISAS_NEXT: Next instruction in program order.
     33 * @DISAS_TOO_MANY: Too many instructions translated.
     34 * @DISAS_NORETURN: Following code is dead.
     35 * @DISAS_TARGET_*: Start of target-specific conditions.
     36 *
     37 * What instruction to disassemble next.
     38 */
     39typedef enum DisasJumpType {
     40    DISAS_NEXT,
     41    DISAS_TOO_MANY,
     42    DISAS_NORETURN,
     43    DISAS_TARGET_0,
     44    DISAS_TARGET_1,
     45    DISAS_TARGET_2,
     46    DISAS_TARGET_3,
     47    DISAS_TARGET_4,
     48    DISAS_TARGET_5,
     49    DISAS_TARGET_6,
     50    DISAS_TARGET_7,
     51    DISAS_TARGET_8,
     52    DISAS_TARGET_9,
     53    DISAS_TARGET_10,
     54    DISAS_TARGET_11,
     55} DisasJumpType;
     56
     57/**
     58 * DisasContextBase:
     59 * @tb: Translation block for this disassembly.
     60 * @pc_first: Address of first guest instruction in this TB.
     61 * @pc_next: Address of next guest instruction in this TB (current during
     62 *           disassembly).
     63 * @is_jmp: What instruction to disassemble next.
     64 * @num_insns: Number of translated instructions (including current).
     65 * @max_insns: Maximum number of instructions to be translated in this TB.
     66 * @singlestep_enabled: "Hardware" single stepping enabled.
     67 *
     68 * Architecture-agnostic disassembly context.
     69 */
     70typedef struct DisasContextBase {
     71    const TranslationBlock *tb;
     72    target_ulong pc_first;
     73    target_ulong pc_next;
     74    DisasJumpType is_jmp;
     75    int num_insns;
     76    int max_insns;
     77    bool singlestep_enabled;
     78#ifdef CONFIG_USER_ONLY
     79    /*
     80     * Guest address of the last byte of the last protected page.
     81     *
     82     * Pages containing the translated instructions are made non-writable in
     83     * order to achieve consistency in case another thread is modifying the
     84     * code while translate_insn() fetches the instruction bytes piecemeal.
     85     * Such writer threads are blocked on mmap_lock() in page_unprotect().
     86     */
     87    target_ulong page_protect_end;
     88#endif
     89} DisasContextBase;
     90
     91/**
     92 * TranslatorOps:
     93 * @init_disas_context:
     94 *      Initialize the target-specific portions of DisasContext struct.
     95 *      The generic DisasContextBase has already been initialized.
     96 *
     97 * @tb_start:
     98 *      Emit any code required before the start of the main loop,
     99 *      after the generic gen_tb_start().
    100 *
    101 * @insn_start:
    102 *      Emit the tcg_gen_insn_start opcode.
    103 *
    104 * @translate_insn:
    105 *      Disassemble one instruction and set db->pc_next for the start
    106 *      of the following instruction.  Set db->is_jmp as necessary to
    107 *      terminate the main loop.
    108 *
    109 * @tb_stop:
    110 *      Emit any opcodes required to exit the TB, based on db->is_jmp.
    111 *
    112 * @disas_log:
    113 *      Print instruction disassembly to log.
    114 */
    115typedef struct TranslatorOps {
    116    void (*init_disas_context)(DisasContextBase *db, CPUState *cpu);
    117    void (*tb_start)(DisasContextBase *db, CPUState *cpu);
    118    void (*insn_start)(DisasContextBase *db, CPUState *cpu);
    119    void (*translate_insn)(DisasContextBase *db, CPUState *cpu);
    120    void (*tb_stop)(DisasContextBase *db, CPUState *cpu);
    121    void (*disas_log)(const DisasContextBase *db, CPUState *cpu);
    122} TranslatorOps;
    123
    124/**
    125 * translator_loop:
    126 * @ops: Target-specific operations.
    127 * @db: Disassembly context.
    128 * @cpu: Target vCPU.
    129 * @tb: Translation block.
    130 * @max_insns: Maximum number of insns to translate.
    131 *
    132 * Generic translator loop.
    133 *
    134 * Translation will stop in the following cases (in order):
    135 * - When is_jmp set by #TranslatorOps::breakpoint_check.
    136 *   - set to DISAS_TOO_MANY exits after translating one more insn
    137 *   - set to any other value than DISAS_NEXT exits immediately.
    138 * - When is_jmp set by #TranslatorOps::translate_insn.
    139 *   - set to any value other than DISAS_NEXT exits immediately.
    140 * - When the TCG operation buffer is full.
    141 * - When single-stepping is enabled (system-wide or on the current vCPU).
    142 * - When too many instructions have been translated.
    143 */
    144void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
    145                     CPUState *cpu, TranslationBlock *tb, int max_insns);
    146
    147void translator_loop_temp_check(DisasContextBase *db);
    148
    149/**
    150 * translator_use_goto_tb
    151 * @db: Disassembly context
    152 * @dest: target pc of the goto
    153 *
    154 * Return true if goto_tb is allowed between the current TB
    155 * and the destination PC.
    156 */
    157bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
    158
    159/*
    160 * Translator Load Functions
    161 *
    162 * These are intended to replace the direct usage of the cpu_ld*_code
    163 * functions and are mandatory for front-ends that have been migrated
    164 * to the common translator_loop. These functions are only intended
    165 * to be called from the translation stage and should not be called
    166 * from helper functions. Those functions should be converted to encode
    167 * the relevant information at translation time.
    168 */
    169
    170#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn)             \
    171    type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
    172                           abi_ptr pc, bool do_swap);                   \
    173    static inline type fullname(CPUArchState *env,                      \
    174                                DisasContextBase *dcbase, abi_ptr pc)   \
    175    {                                                                   \
    176        return fullname ## _swap(env, dcbase, pc, false);               \
    177    }
    178
    179#define FOR_EACH_TRANSLATOR_LD(F)                                       \
    180    F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */)           \
    181    F(translator_ldsw, int16_t, cpu_ldsw_code, bswap16)                 \
    182    F(translator_lduw, uint16_t, cpu_lduw_code, bswap16)                \
    183    F(translator_ldl, uint32_t, cpu_ldl_code, bswap32)                  \
    184    F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
    185
    186FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
    187
    188#undef GEN_TRANSLATOR_LD
    189
    190#endif  /* EXEC__TRANSLATOR_H */