cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

ich9.h (2963B)

      1/*
      2 * QEMU GMCH/ICH9 LPC PM Emulation
      3 *
      4 *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
      5 *                     VA Linux Systems Japan K.K.
      6 *
      7 * This library is free software; you can redistribute it and/or
      8 * modify it under the terms of the GNU Lesser General Public
      9 * License as published by the Free Software Foundation; either
     10 * version 2.1 of the License, or (at your option) any later version.
     11 *
     12 * This library is distributed in the hope that it will be useful,
     13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     15 * Lesser General Public License for more details.
     16 *
     17 * You should have received a copy of the GNU Lesser General Public
     18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
     19 */
     20
     21#ifndef HW_ACPI_ICH9_H
     22#define HW_ACPI_ICH9_H
     23
     24#include "hw/acpi/acpi.h"
     25#include "hw/acpi/cpu_hotplug.h"
     26#include "hw/acpi/cpu.h"
     27#include "hw/acpi/pcihp.h"
     28#include "hw/acpi/memory_hotplug.h"
     29#include "hw/acpi/acpi_dev_interface.h"
     30#include "hw/acpi/tco.h"
     31
     32#define ACPI_PCIHP_ADDR_ICH9 0x0cc0
     33
     34typedef struct ICH9LPCPMRegs {
     35    /*
     36     * In ich9 spec says that pm1_cnt register is 32bit width and
     37     * that the upper 16bits are reserved and unused.
     38     * PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
     39     */
     40    ACPIREGS acpi_regs;
     41
     42    MemoryRegion io;
     43    MemoryRegion io_gpe;
     44    MemoryRegion io_smi;
     45
     46    uint32_t smi_en;
     47    uint32_t smi_en_wmask;
     48    uint32_t smi_sts;
     49
     50    qemu_irq irq;      /* SCI */
     51
     52    uint32_t pm_io_base;
     53    Notifier powerdown_notifier;
     54
     55    bool cpu_hotplug_legacy;
     56    AcpiCpuHotplug gpe_cpu;
     57    CPUHotplugState cpuhp_state;
     58
     59    bool use_acpi_hotplug_bridge;
     60    AcpiPciHpState acpi_pci_hotplug;
     61    MemHotplugState acpi_memory_hotplug;
     62
     63    uint8_t disable_s3;
     64    uint8_t disable_s4;
     65    uint8_t s4_val;
     66    uint8_t smm_enabled;
     67    bool smm_compat;
     68    bool enable_tco;
     69    TCOIORegs tco_regs;
     70} ICH9LPCPMRegs;
     71
     72#define ACPI_PM_PROP_TCO_ENABLED "enable_tco"
     73
     74void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
     75                  bool smm_enabled,
     76                  qemu_irq sci_irq);
     77
     78void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
     79extern const VMStateDescription vmstate_ich9_pm;
     80
     81void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm);
     82
     83void ich9_pm_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
     84                                Error **errp);
     85void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
     86                            Error **errp);
     87void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev,
     88                                      DeviceState *dev, Error **errp);
     89void ich9_pm_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
     90                              Error **errp);
     91
     92void ich9_pm_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list);
     93#endif /* HW_ACPI_ICH9_H */