cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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tco.h (1900B)

      1/*
      2 * QEMU ICH9 TCO emulation
      3 *
      4 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
      5 *
      6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
      7 * See the COPYING file in the top-level directory.
      8 */
      9
     10#ifndef HW_ACPI_TCO_H
     11#define HW_ACPI_TCO_H
     12
     13#include "exec/memory.h"
     14
     15/* As per ICH9 spec, the internal timer has an error of ~0.6s on every tick */
     16#define TCO_TICK_NSEC 600000000LL
     17
     18/* TCO I/O register offsets */
     19enum {
     20    TCO_RLD           = 0x00,
     21    TCO_DAT_IN        = 0x02,
     22    TCO_DAT_OUT       = 0x03,
     23    TCO1_STS          = 0x04,
     24    TCO2_STS          = 0x06,
     25    TCO1_CNT          = 0x08,
     26    TCO2_CNT          = 0x0a,
     27    TCO_MESSAGE1      = 0x0c,
     28    TCO_MESSAGE2      = 0x0d,
     29    TCO_WDCNT         = 0x0e,
     30    SW_IRQ_GEN        = 0x10,
     31    TCO_TMR           = 0x12,
     32};
     33
     34/* TCO I/O register control/status bits */
     35enum {
     36    SW_TCO_SMI           = 1 << 1,
     37    TCO_INT_STS          = 1 << 2,
     38    TCO_LOCK             = 1 << 12,
     39    TCO_TMR_HLT          = 1 << 11,
     40    TCO_TIMEOUT          = 1 << 3,
     41    TCO_SECOND_TO_STS    = 1 << 1,
     42    TCO_BOOT_STS         = 1 << 2,
     43};
     44
     45/* TCO I/O registers mask bits */
     46enum {
     47    TCO_RLD_MASK     = 0x3ff,
     48    TCO1_STS_MASK    = 0xe870,
     49    TCO2_STS_MASK    = 0xfff8,
     50    TCO1_CNT_MASK    = 0xfeff,
     51    TCO_TMR_MASK     = 0x3ff,
     52};
     53
     54typedef struct TCOIORegs {
     55    struct {
     56        uint16_t rld;
     57        uint8_t din;
     58        uint8_t dout;
     59        uint16_t sts1;
     60        uint16_t sts2;
     61        uint16_t cnt1;
     62        uint16_t cnt2;
     63        uint8_t msg1;
     64        uint8_t msg2;
     65        uint8_t wdcnt;
     66        uint16_t tmr;
     67    } tco;
     68    uint8_t sw_irq_gen;
     69
     70    QEMUTimer *tco_timer;
     71    int64_t expire_time;
     72    uint8_t timeouts_no;
     73
     74    MemoryRegion io;
     75} TCOIORegs;
     76
     77/* tco.c */
     78void acpi_pm_tco_init(TCOIORegs *tr, MemoryRegion *parent);
     79
     80extern const VMStateDescription vmstate_tco_io_sts;
     81
     82#endif /* HW_ACPI_TCO_H */