cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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nrf51.h (1306B)


      1/*
      2 * Nordic Semiconductor nRF51 Series SOC Common Defines
      3 *
      4 * This file hosts generic defines used in various nRF51 peripheral devices.
      5 *
      6 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
      7 * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf
      8 *
      9 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
     10 *
     11 * This code is licensed under the GPL version 2 or later.  See
     12 * the COPYING file in the top-level directory.
     13 */
     14
     15#ifndef NRF51_H
     16#define NRF51_H
     17
     18#define NRF51_FLASH_BASE      0x00000000
     19#define NRF51_FICR_BASE       0x10000000
     20#define NRF51_FICR_SIZE       0x00000100
     21#define NRF51_UICR_BASE       0x10001000
     22#define NRF51_SRAM_BASE       0x20000000
     23
     24#define NRF51_IOMEM_BASE      0x40000000
     25#define NRF51_IOMEM_SIZE      0x20000000
     26
     27#define NRF51_PERIPHERAL_SIZE 0x00001000
     28#define NRF51_UART_BASE       0x40002000
     29#define NRF51_TWI_BASE        0x40003000
     30#define NRF51_TIMER_BASE      0x40008000
     31#define NRF51_RNG_BASE        0x4000D000
     32#define NRF51_NVMC_BASE       0x4001E000
     33#define NRF51_GPIO_BASE       0x50000000
     34
     35#define NRF51_PRIVATE_BASE    0xF0000000
     36#define NRF51_PRIVATE_SIZE    0x10000000
     37
     38#define NRF51_PAGE_SIZE       1024
     39
     40/* Trigger */
     41#define NRF51_TRIGGER_TASK 0x01
     42
     43/* Events */
     44#define NRF51_EVENT_CLEAR  0x00
     45
     46#endif