cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

xlnx-zynqmp.h (4162B)

      1/*
      2 * Xilinx Zynq MPSoC emulation
      3 *
      4 * Copyright (C) 2015 Xilinx Inc
      5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
      6 *
      7 * This program is free software; you can redistribute it and/or modify it
      8 * under the terms of the GNU General Public License as published by the
      9 * Free Software Foundation; either version 2 of the License, or
     10 * (at your option) any later version.
     11 *
     12 * This program is distributed in the hope that it will be useful, but WITHOUT
     13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
     15 * for more details.
     16 */
     17
     18#ifndef XLNX_ZYNQMP_H
     19#define XLNX_ZYNQMP_H
     20
     21#include "hw/arm/boot.h"
     22#include "hw/intc/arm_gic.h"
     23#include "hw/net/cadence_gem.h"
     24#include "hw/char/cadence_uart.h"
     25#include "hw/net/xlnx-zynqmp-can.h"
     26#include "hw/ide/ahci.h"
     27#include "hw/sd/sdhci.h"
     28#include "hw/ssi/xilinx_spips.h"
     29#include "hw/dma/xlnx_dpdma.h"
     30#include "hw/dma/xlnx-zdma.h"
     31#include "hw/display/xlnx_dp.h"
     32#include "hw/intc/xlnx-zynqmp-ipi.h"
     33#include "hw/rtc/xlnx-zynqmp-rtc.h"
     34#include "hw/cpu/cluster.h"
     35#include "target/arm/cpu.h"
     36#include "qom/object.h"
     37#include "net/can_emu.h"
     38#include "hw/dma/xlnx_csu_dma.h"
     39#include "hw/nvram/xlnx-bbram.h"
     40#include "hw/nvram/xlnx-zynqmp-efuse.h"
     41
     42#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
     43OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
     44
     45#define XLNX_ZYNQMP_NUM_APU_CPUS 4
     46#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
     47#define XLNX_ZYNQMP_NUM_GEMS 4
     48#define XLNX_ZYNQMP_NUM_UARTS 2
     49#define XLNX_ZYNQMP_NUM_CAN 2
     50#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
     51#define XLNX_ZYNQMP_NUM_SDHCI 2
     52#define XLNX_ZYNQMP_NUM_SPIS 2
     53#define XLNX_ZYNQMP_NUM_GDMA_CH 8
     54#define XLNX_ZYNQMP_NUM_ADMA_CH 8
     55
     56#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
     57#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
     58#define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
     59
     60#define XLNX_ZYNQMP_NUM_OCM_BANKS 4
     61#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
     62#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
     63
     64#define XLNX_ZYNQMP_GIC_REGIONS 6
     65
     66/*
     67 * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
     68 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
     69 * aligned address in the 64k region. To implement each GIC region needs a
     70 * number of memory region aliases.
     71 */
     72
     73#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
     74#define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
     75
     76#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE    0x80000000ull
     77
     78#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE   0x800000000ull
     79#define XLNX_ZYNQMP_HIGH_RAM_START      0x800000000ull
     80
     81#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
     82                                  XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
     83
     84/*
     85 * Unimplemented mmio regions needed to boot some images.
     86 */
     87#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
     88
     89struct XlnxZynqMPState {
     90    /*< private >*/
     91    DeviceState parent_obj;
     92
     93    /*< public >*/
     94    CPUClusterState apu_cluster;
     95    CPUClusterState rpu_cluster;
     96    ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
     97    ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
     98    GICState gic;
     99    MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
    100
    101    MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
    102
    103    MemoryRegion *ddr_ram;
    104    MemoryRegion ddr_ram_low, ddr_ram_high;
    105    XlnxBBRam bbram;
    106    XlnxEFuse efuse;
    107    XlnxZynqMPEFuse efuse_ctrl;
    108
    109    MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
    110
    111    CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
    112    CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
    113    XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
    114    SysbusAHCIState sata;
    115    SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
    116    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
    117    XlnxZynqMPQSPIPS qspi;
    118    XlnxDPState dp;
    119    XlnxDPDMAState dpdma;
    120    XlnxZynqMPIPI ipi;
    121    XlnxZynqMPRTC rtc;
    122    XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
    123    XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
    124    XlnxCSUDMA qspi_dma;
    125
    126    char *boot_cpu;
    127    ARMCPU *boot_cpu_ptr;
    128
    129    /* Has the ARM Security extensions?  */
    130    bool secure;
    131    /* Has the ARM Virtualization extensions?  */
    132    bool virt;
    133
    134    /* CAN bus. */
    135    CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
    136};
    137
    138#endif