cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

ibex_uart.h (2234B)

      1/*
      2 * QEMU lowRISC Ibex UART device
      3 *
      4 * Copyright (c) 2020 Western Digital
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25#ifndef HW_IBEX_UART_H
     26#define HW_IBEX_UART_H
     27
     28#include "hw/sysbus.h"
     29#include "hw/registerfields.h"
     30#include "chardev/char-fe.h"
     31#include "qemu/timer.h"
     32#include "qom/object.h"
     33
     34#define IBEX_UART_TX_FIFO_SIZE 16
     35#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
     36
     37#define TYPE_IBEX_UART "ibex-uart"
     38OBJECT_DECLARE_SIMPLE_TYPE(IbexUartState, IBEX_UART)
     39
     40struct IbexUartState {
     41    /* <private> */
     42    SysBusDevice parent_obj;
     43
     44    /* <public> */
     45    MemoryRegion mmio;
     46
     47    uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE];
     48    uint32_t tx_level;
     49
     50    uint32_t rx_level;
     51
     52    QEMUTimer *fifo_trigger_handle;
     53    uint64_t char_tx_time;
     54
     55    uint32_t uart_intr_state;
     56    uint32_t uart_intr_enable;
     57    uint32_t uart_ctrl;
     58    uint32_t uart_status;
     59    uint32_t uart_rdata;
     60    uint32_t uart_fifo_ctrl;
     61    uint32_t uart_fifo_status;
     62    uint32_t uart_ovrd;
     63    uint32_t uart_val;
     64    uint32_t uart_timeout_ctrl;
     65
     66    Clock *f_clk;
     67
     68    CharBackend chr;
     69    qemu_irq tx_watermark;
     70    qemu_irq rx_watermark;
     71    qemu_irq tx_empty;
     72    qemu_irq rx_overflow;
     73};
     74#endif /* HW_IBEX_UART_H */