cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

mchp_pfsoc_mmuart.h (2344B)

      1/*
      2 * Microchip PolarFire SoC MMUART emulation
      3 *
      4 * Copyright (c) 2020 Wind River Systems, Inc.
      5 *
      6 * Author:
      7 *   Bin Meng <bin.meng@windriver.com>
      8 *
      9 * Permission is hereby granted, free of charge, to any person obtaining a copy
     10 * of this software and associated documentation files (the "Software"), to deal
     11 * in the Software without restriction, including without limitation the rights
     12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     13 * copies of the Software, and to permit persons to whom the Software is
     14 * furnished to do so, subject to the following conditions:
     15 *
     16 * The above copyright notice and this permission notice shall be included in
     17 * all copies or substantial portions of the Software.
     18 *
     19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     25 * THE SOFTWARE.
     26 */
     27
     28#ifndef HW_MCHP_PFSOC_MMUART_H
     29#define HW_MCHP_PFSOC_MMUART_H
     30
     31#include "hw/sysbus.h"
     32#include "hw/char/serial.h"
     33
     34#define MCHP_PFSOC_MMUART_REG_COUNT 13
     35
     36#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
     37OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
     38
     39typedef struct MchpPfSoCMMUartState {
     40    /*< private >*/
     41    SysBusDevice parent_obj;
     42
     43    /*< public >*/
     44    MemoryRegion container;
     45    MemoryRegion iomem;
     46
     47    SerialMM serial_mm;
     48
     49    uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
     50} MchpPfSoCMMUartState;
     51
     52/**
     53 * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
     54 *
     55 * This is a helper routine for board to create a MMUART device that is
     56 * compatible with Microchip PolarFire SoC.
     57 *
     58 * @sysmem: system memory region to map
     59 * @base: base address of the MMUART registers
     60 * @irq: IRQ number of the MMUART device
     61 * @chr: character device to associate to
     62 *
     63 * @return: a pointer to the device specific control structure
     64 */
     65MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
     66    hwaddr base, qemu_irq irq, Chardev *chr);
     67
     68#endif /* HW_MCHP_PFSOC_MMUART_H */