cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

xlnx_csu_dma.h (1498B)

      1/*
      2 * Xilinx Platform CSU Stream DMA emulation
      3 *
      4 * This implementation is based on
      5 * https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c
      6 *
      7 * This program is free software; you can redistribute it and/or
      8 * modify it under the terms of the GNU General Public License as
      9 * published by the Free Software Foundation; either version 2 or
     10 * (at your option) version 3 of the License.
     11 *
     12 * This program is distributed in the hope that it will be useful,
     13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
     15 * GNU General Public License for more details.
     16 *
     17 * You should have received a copy of the GNU General Public License along
     18 * with this program; if not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21#ifndef XLNX_CSU_DMA_H
     22#define XLNX_CSU_DMA_H
     23
     24#define TYPE_XLNX_CSU_DMA "xlnx.csu_dma"
     25
     26#define XLNX_CSU_DMA_R_MAX (0x2c / 4)
     27
     28typedef struct XlnxCSUDMA {
     29    SysBusDevice busdev;
     30    MemoryRegion iomem;
     31    MemTxAttrs attr;
     32    MemoryRegion *dma_mr;
     33    AddressSpace dma_as;
     34    qemu_irq irq;
     35    StreamSink *tx_dev; /* Used as generic StreamSink */
     36    ptimer_state *src_timer;
     37
     38    uint16_t width;
     39    bool is_dst;
     40    bool r_size_last_word;
     41
     42    StreamCanPushNotifyFn notify;
     43    void *notify_opaque;
     44
     45    uint32_t regs[XLNX_CSU_DMA_R_MAX];
     46    RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX];
     47} XlnxCSUDMA;
     48
     49#define XLNX_CSU_DMA(obj) \
     50    OBJECT_CHECK(XlnxCSUDMA, (obj), TYPE_XLNX_CSU_DMA)
     51
     52#endif