cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

aspeed_gpio.h (2449B)

      1/*
      2 *  ASPEED GPIO Controller
      3 *
      4 *  Copyright (C) 2017-2018 IBM Corp.
      5 *
      6 * This code is licensed under the GPL version 2 or later.  See
      7 * the COPYING file in the top-level directory.
      8 */
      9
     10#ifndef ASPEED_GPIO_H
     11#define ASPEED_GPIO_H
     12
     13#include "hw/sysbus.h"
     14#include "qom/object.h"
     15
     16#define TYPE_ASPEED_GPIO "aspeed.gpio"
     17OBJECT_DECLARE_TYPE(AspeedGPIOState, AspeedGPIOClass, ASPEED_GPIO)
     18
     19#define ASPEED_GPIO_MAX_NR_SETS 8
     20#define ASPEED_GPIOS_PER_SET 32
     21#define ASPEED_REGS_PER_BANK 14
     22#define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS)
     23#define ASPEED_GROUPS_PER_SET 4
     24#define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
     25#define ASPEED_CHARS_PER_GROUP_LABEL 4
     26
     27typedef struct GPIOSets GPIOSets;
     28
     29typedef struct GPIOSetProperties {
     30    uint32_t input;
     31    uint32_t output;
     32    char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
     33} GPIOSetProperties;
     34
     35enum GPIORegType {
     36    gpio_not_a_reg,
     37    gpio_reg_data_value,
     38    gpio_reg_direction,
     39    gpio_reg_int_enable,
     40    gpio_reg_int_sens_0,
     41    gpio_reg_int_sens_1,
     42    gpio_reg_int_sens_2,
     43    gpio_reg_int_status,
     44    gpio_reg_reset_tolerant,
     45    gpio_reg_debounce_1,
     46    gpio_reg_debounce_2,
     47    gpio_reg_cmd_source_0,
     48    gpio_reg_cmd_source_1,
     49    gpio_reg_data_read,
     50    gpio_reg_input_mask,
     51};
     52
     53typedef struct AspeedGPIOReg {
     54    uint16_t set_idx;
     55    enum GPIORegType type;
     56 } AspeedGPIOReg;
     57
     58struct AspeedGPIOClass {
     59    SysBusDevice parent_obj;
     60    const GPIOSetProperties *props;
     61    uint32_t nr_gpio_pins;
     62    uint32_t nr_gpio_sets;
     63    const AspeedGPIOReg *reg_table;
     64};
     65
     66struct AspeedGPIOState {
     67    /* <private> */
     68    SysBusDevice parent;
     69
     70    /*< public >*/
     71    MemoryRegion iomem;
     72    int pending;
     73    qemu_irq irq;
     74    qemu_irq gpios[ASPEED_GPIO_MAX_NR_SETS][ASPEED_GPIOS_PER_SET];
     75
     76/* Parallel GPIO Registers */
     77    uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
     78    struct GPIOSets {
     79        uint32_t data_value; /* Reflects pin values */
     80        uint32_t data_read; /* Contains last value written to data value */
     81        uint32_t direction;
     82        uint32_t int_enable;
     83        uint32_t int_sens_0;
     84        uint32_t int_sens_1;
     85        uint32_t int_sens_2;
     86        uint32_t int_status;
     87        uint32_t reset_tol;
     88        uint32_t cmd_source_0;
     89        uint32_t cmd_source_1;
     90        uint32_t debounce_1;
     91        uint32_t debounce_2;
     92        uint32_t input_mask;
     93    } sets[ASPEED_GPIO_MAX_NR_SETS];
     94};
     95
     96#endif /* _ASPEED_GPIO_H_ */