cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

imx_gpio.h (1918B)

      1/*
      2 * i.MX processors GPIO registers definition.
      3 *
      4 * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
      5 *
      6 * This program is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU General Public License as
      8 * published by the Free Software Foundation; either version 2 or
      9 * (at your option) version 3 of the License.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License along
     17 * with this program; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef IMX_GPIO_H
     21#define IMX_GPIO_H
     22
     23#include "hw/sysbus.h"
     24#include "qom/object.h"
     25
     26#define TYPE_IMX_GPIO "imx.gpio"
     27OBJECT_DECLARE_SIMPLE_TYPE(IMXGPIOState, IMX_GPIO)
     28
     29#define IMX_GPIO_MEM_SIZE 0x20
     30
     31/* i.MX GPIO memory map */
     32#define DR_ADDR             0x00 /* DATA REGISTER */
     33#define GDIR_ADDR           0x04 /* DIRECTION REGISTER */
     34#define PSR_ADDR            0x08 /* PAD STATUS REGISTER */
     35#define ICR1_ADDR           0x0c /* INTERRUPT CONFIGURATION REGISTER 1 */
     36#define ICR2_ADDR           0x10 /* INTERRUPT CONFIGURATION REGISTER 2 */
     37#define IMR_ADDR            0x14 /* INTERRUPT MASK REGISTER */
     38#define ISR_ADDR            0x18 /* INTERRUPT STATUS REGISTER */
     39#define EDGE_SEL_ADDR       0x1c /* EDGE SEL REGISTER */
     40
     41#define IMX_GPIO_PIN_COUNT 32
     42
     43struct IMXGPIOState {
     44    /*< private >*/
     45    SysBusDevice parent_obj;
     46
     47    /*< public >*/
     48    MemoryRegion iomem;
     49
     50    uint32_t dr;
     51    uint32_t gdir;
     52    uint32_t psr;
     53    uint64_t icr;
     54    uint32_t imr;
     55    uint32_t isr;
     56    bool has_edge_sel;
     57    uint32_t edge_sel;
     58    bool has_upper_pin_irq;
     59
     60    qemu_irq irq[2];
     61    qemu_irq output[IMX_GPIO_PIN_COUNT];
     62};
     63
     64#endif /* IMX_GPIO_H */