cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

imx_i2c.h (2689B)

      1/*
      2 *  i.MX I2C Bus Serial Interface registers definition
      3 *
      4 *  Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
      5 *
      6 *  This program is free software; you can redistribute it and/or modify it
      7 *  under the terms of the GNU General Public License as published by the
      8 *  Free Software Foundation; either version 2 of the License, or
      9 *  (at your option) any later version.
     10 *
     11 *  This program is distributed in the hope that it will be useful, but WITHOUT
     12 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     13 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
     14 *  for more details.
     15 *
     16 *  You should have received a copy of the GNU General Public License along
     17 *  with this program; if not, see <http://www.gnu.org/licenses/>.
     18 *
     19 */
     20
     21#ifndef IMX_I2C_H
     22#define IMX_I2C_H
     23
     24#include "hw/sysbus.h"
     25#include "qom/object.h"
     26
     27#define TYPE_IMX_I2C "imx.i2c"
     28OBJECT_DECLARE_SIMPLE_TYPE(IMXI2CState, IMX_I2C)
     29
     30#define IMX_I2C_MEM_SIZE           0x14
     31
     32/* i.MX I2C memory map */
     33#define IADR_ADDR                  0x00  /* address register */
     34#define IFDR_ADDR                  0x04  /* frequency divider register */
     35#define I2CR_ADDR                  0x08  /* control register */
     36#define I2SR_ADDR                  0x0c  /* status register */
     37#define I2DR_ADDR                  0x10  /* data register */
     38
     39#define IADR_MASK                  0xFE
     40#define IADR_RESET                 0
     41
     42#define IFDR_MASK                  0x3F
     43#define IFDR_RESET                 0
     44
     45#define I2CR_IEN                   (1 << 7)
     46#define I2CR_IIEN                  (1 << 6)
     47#define I2CR_MSTA                  (1 << 5)
     48#define I2CR_MTX                   (1 << 4)
     49#define I2CR_TXAK                  (1 << 3)
     50#define I2CR_RSTA                  (1 << 2)
     51#define I2CR_MASK                  0xFC
     52#define I2CR_RESET                 0
     53
     54#define I2SR_ICF                   (1 << 7)
     55#define I2SR_IAAF                  (1 << 6)
     56#define I2SR_IBB                   (1 << 5)
     57#define I2SR_IAL                   (1 << 4)
     58#define I2SR_SRW                   (1 << 2)
     59#define I2SR_IIF                   (1 << 1)
     60#define I2SR_RXAK                  (1 << 0)
     61#define I2SR_MASK                  0xE9
     62#define I2SR_RESET                 0x81
     63
     64#define I2DR_MASK                  0xFF
     65#define I2DR_RESET                 0
     66
     67#define ADDR_RESET                 0xFF00
     68
     69struct IMXI2CState {
     70    /*< private >*/
     71    SysBusDevice parent_obj;
     72
     73    /*< public >*/
     74    MemoryRegion iomem;
     75    I2CBus *bus;
     76    qemu_irq irq;
     77
     78    uint16_t  address;
     79
     80    uint16_t iadr;
     81    uint16_t ifdr;
     82    uint16_t i2cr;
     83    uint16_t i2sr;
     84    uint16_t i2dr_read;
     85    uint16_t i2dr_write;
     86};
     87
     88#endif /* IMX_I2C_H */