cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

pc.h (9973B)

      1#ifndef HW_PC_H
      2#define HW_PC_H
      3
      4#include "qemu/notify.h"
      5#include "qapi/qapi-types-common.h"
      6#include "qemu/uuid.h"
      7#include "hw/boards.h"
      8#include "hw/block/fdc.h"
      9#include "hw/block/flash.h"
     10#include "hw/i386/x86.h"
     11
     12#include "hw/acpi/acpi_dev_interface.h"
     13#include "hw/hotplug.h"
     14#include "qom/object.h"
     15#include "hw/i386/sgx-epc.h"
     16
     17#define HPET_INTCAP "hpet-intcap"
     18
     19/**
     20 * PCMachineState:
     21 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
     22 * @boot_cpus: number of present VCPUs
     23 */
     24typedef struct PCMachineState {
     25    /*< private >*/
     26    X86MachineState parent_obj;
     27
     28    /* <public> */
     29
     30    /* State for other subsystems/APIs: */
     31    Notifier machine_done;
     32
     33    /* Pointers to devices and objects: */
     34    PCIBus *bus;
     35    I2CBus *smbus;
     36    PFlashCFI01 *flash[2];
     37    ISADevice *pcspk;
     38
     39    /* Configuration options: */
     40    uint64_t max_ram_below_4g;
     41    OnOffAuto vmport;
     42
     43    bool acpi_build_enabled;
     44    bool smbus_enabled;
     45    bool sata_enabled;
     46    bool pit_enabled;
     47    bool hpet_enabled;
     48    bool default_bus_bypass_iommu;
     49    uint64_t max_fw_size;
     50
     51    /* ACPI Memory hotplug IO base address */
     52    hwaddr memhp_io_base;
     53
     54    SGXEPCState sgx_epc;
     55} PCMachineState;
     56
     57#define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
     58#define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g"
     59#define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size"
     60#define PC_MACHINE_VMPORT           "vmport"
     61#define PC_MACHINE_SMBUS            "smbus"
     62#define PC_MACHINE_SATA             "sata"
     63#define PC_MACHINE_PIT              "pit"
     64#define PC_MACHINE_MAX_FW_SIZE      "max-fw-size"
     65/**
     66 * PCMachineClass:
     67 *
     68 * Compat fields:
     69 *
     70 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by
     71 *                        backend's alignment value if provided
     72 * @acpi_data_size: Size of the chunk of memory at the top of RAM
     73 *                  for the BIOS ACPI tables and other BIOS
     74 *                  datastructures.
     75 * @gigabyte_align: Make sure that guest addresses aligned at
     76 *                  1Gbyte boundaries get mapped to host
     77 *                  addresses aligned at 1Gbyte boundaries. This
     78 *                  way we can use 1GByte pages in the host.
     79 *
     80 */
     81struct PCMachineClass {
     82    /*< private >*/
     83    X86MachineClass parent_class;
     84
     85    /*< public >*/
     86
     87    /* Device configuration: */
     88    bool pci_enabled;
     89    bool kvmclock_enabled;
     90    const char *default_nic_model;
     91
     92    /* Compat options: */
     93
     94    /* Default CPU model version.  See x86_cpu_set_default_version(). */
     95    int default_cpu_version;
     96
     97    /* ACPI compat: */
     98    bool has_acpi_build;
     99    bool rsdp_in_ram;
    100    int legacy_acpi_table_size;
    101    unsigned acpi_data_size;
    102    bool do_not_add_smb_acpi;
    103    int pci_root_uid;
    104
    105    /* SMBIOS compat: */
    106    bool smbios_defaults;
    107    bool smbios_legacy_mode;
    108    bool smbios_uuid_encoded;
    109
    110    /* RAM / address space compat: */
    111    bool gigabyte_align;
    112    bool has_reserved_memory;
    113    bool enforce_aligned_dimm;
    114    bool broken_reserved_end;
    115
    116    /* generate legacy CPU hotplug AML */
    117    bool legacy_cpu_hotplug;
    118
    119    /* use DMA capable linuxboot option rom */
    120    bool linuxboot_dma_enabled;
    121
    122    /* use PVH to load kernels that support this feature */
    123    bool pvh_enabled;
    124
    125    /* create kvmclock device even when KVM PV features are not exposed */
    126    bool kvmclock_create_always;
    127};
    128
    129#define TYPE_PC_MACHINE "generic-pc-machine"
    130OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE)
    131
    132/* ioapic.c */
    133
    134GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled);
    135
    136/* pc.c */
    137extern int fd_bootchk;
    138
    139void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
    140
    141void pc_guest_info_init(PCMachineState *pcms);
    142
    143#define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
    144#define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
    145#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
    146#define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
    147#define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
    148#define PCI_HOST_BELOW_4G_MEM_SIZE     "below-4g-mem-size"
    149#define PCI_HOST_ABOVE_4G_MEM_SIZE     "above-4g-mem-size"
    150
    151typedef enum {
    152    SEV_DESC_TYPE_UNDEF,
    153    /* The section contains the region that must be validated by the VMM. */
    154    SEV_DESC_TYPE_SNP_SEC_MEM,
    155    /* The section contains the SNP secrets page */
    156    SEV_DESC_TYPE_SNP_SECRETS,
    157    /* The section contains address that can be used as a CPUID page */
    158    SEV_DESC_TYPE_CPUID,
    159
    160} ovmf_sev_metadata_desc_type;
    161
    162typedef struct __attribute__((__packed__)) OvmfSevMetadataDesc {
    163    uint32_t base;
    164    uint32_t len;
    165    ovmf_sev_metadata_desc_type type;
    166} OvmfSevMetadataDesc;
    167
    168typedef struct __attribute__((__packed__)) OvmfSevMetadata {
    169    uint8_t signature[4];
    170    uint32_t len;
    171    uint32_t version;
    172    uint32_t num_desc;
    173    OvmfSevMetadataDesc descs[];
    174} OvmfSevMetadata;
    175
    176OvmfSevMetadata *pc_system_get_ovmf_sev_metadata_ptr(void);
    177
    178void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
    179                            MemoryRegion *pci_address_space);
    180
    181void xen_load_linux(PCMachineState *pcms);
    182void pc_memory_init(PCMachineState *pcms,
    183                    MemoryRegion *system_memory,
    184                    MemoryRegion *rom_memory,
    185                    MemoryRegion **ram_memory);
    186uint64_t pc_pci_hole64_start(void);
    187DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
    188void pc_basic_device_init(struct PCMachineState *pcms,
    189                          ISABus *isa_bus, qemu_irq *gsi,
    190                          ISADevice **rtc_state,
    191                          bool create_fdctrl,
    192                          uint32_t hpet_irqs);
    193void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
    194void pc_cmos_init(PCMachineState *pcms,
    195                  BusState *ide0, BusState *ide1,
    196                  ISADevice *s);
    197void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus);
    198void pc_pci_device_init(PCIBus *pci_bus);
    199
    200typedef void (*cpu_set_smm_t)(int smm, void *arg);
    201
    202void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
    203
    204ISADevice *pc_find_fdc0(void);
    205
    206/* port92.c */
    207#define PORT92_A20_LINE "a20"
    208
    209#define TYPE_PORT92 "port92"
    210
    211/* pc_sysfw.c */
    212void pc_system_flash_create(PCMachineState *pcms);
    213void pc_system_flash_cleanup_unused(PCMachineState *pcms);
    214void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
    215bool pc_system_ovmf_table_find(const char *entry, uint8_t **data,
    216                               int *data_len);
    217void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size);
    218
    219/* hw/i386/acpi-common.c */
    220void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
    221                       const CPUArchIdList *apic_ids, GArray *entry,
    222                       bool force_enabled);
    223
    224/* sgx.c */
    225void pc_machine_init_sgx_epc(PCMachineState *pcms);
    226
    227extern GlobalProperty pc_compat_6_1[];
    228extern const size_t pc_compat_6_1_len;
    229
    230extern GlobalProperty pc_compat_6_0[];
    231extern const size_t pc_compat_6_0_len;
    232
    233extern GlobalProperty pc_compat_5_2[];
    234extern const size_t pc_compat_5_2_len;
    235
    236extern GlobalProperty pc_compat_5_1[];
    237extern const size_t pc_compat_5_1_len;
    238
    239extern GlobalProperty pc_compat_5_0[];
    240extern const size_t pc_compat_5_0_len;
    241
    242extern GlobalProperty pc_compat_4_2[];
    243extern const size_t pc_compat_4_2_len;
    244
    245extern GlobalProperty pc_compat_4_1[];
    246extern const size_t pc_compat_4_1_len;
    247
    248extern GlobalProperty pc_compat_4_0[];
    249extern const size_t pc_compat_4_0_len;
    250
    251extern GlobalProperty pc_compat_3_1[];
    252extern const size_t pc_compat_3_1_len;
    253
    254extern GlobalProperty pc_compat_3_0[];
    255extern const size_t pc_compat_3_0_len;
    256
    257extern GlobalProperty pc_compat_2_12[];
    258extern const size_t pc_compat_2_12_len;
    259
    260extern GlobalProperty pc_compat_2_11[];
    261extern const size_t pc_compat_2_11_len;
    262
    263extern GlobalProperty pc_compat_2_10[];
    264extern const size_t pc_compat_2_10_len;
    265
    266extern GlobalProperty pc_compat_2_9[];
    267extern const size_t pc_compat_2_9_len;
    268
    269extern GlobalProperty pc_compat_2_8[];
    270extern const size_t pc_compat_2_8_len;
    271
    272extern GlobalProperty pc_compat_2_7[];
    273extern const size_t pc_compat_2_7_len;
    274
    275extern GlobalProperty pc_compat_2_6[];
    276extern const size_t pc_compat_2_6_len;
    277
    278extern GlobalProperty pc_compat_2_5[];
    279extern const size_t pc_compat_2_5_len;
    280
    281extern GlobalProperty pc_compat_2_4[];
    282extern const size_t pc_compat_2_4_len;
    283
    284extern GlobalProperty pc_compat_2_3[];
    285extern const size_t pc_compat_2_3_len;
    286
    287extern GlobalProperty pc_compat_2_2[];
    288extern const size_t pc_compat_2_2_len;
    289
    290extern GlobalProperty pc_compat_2_1[];
    291extern const size_t pc_compat_2_1_len;
    292
    293extern GlobalProperty pc_compat_2_0[];
    294extern const size_t pc_compat_2_0_len;
    295
    296extern GlobalProperty pc_compat_1_7[];
    297extern const size_t pc_compat_1_7_len;
    298
    299extern GlobalProperty pc_compat_1_6[];
    300extern const size_t pc_compat_1_6_len;
    301
    302extern GlobalProperty pc_compat_1_5[];
    303extern const size_t pc_compat_1_5_len;
    304
    305extern GlobalProperty pc_compat_1_4[];
    306extern const size_t pc_compat_1_4_len;
    307
    308/* Helper for setting model-id for CPU models that changed model-id
    309 * depending on QEMU versions up to QEMU 2.4.
    310 */
    311#define PC_CPU_MODEL_IDS(v) \
    312    { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
    313    { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\
    314    { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },
    315
    316#define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \
    317    static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \
    318    { \
    319        MachineClass *mc = MACHINE_CLASS(oc); \
    320        optsfn(mc); \
    321        mc->init = initfn; \
    322    } \
    323    static const TypeInfo pc_machine_type_##suffix = { \
    324        .name       = namestr TYPE_MACHINE_SUFFIX, \
    325        .parent     = TYPE_PC_MACHINE, \
    326        .class_init = pc_machine_##suffix##_class_init, \
    327    }; \
    328    static void pc_machine_init_##suffix(void) \
    329    { \
    330        type_register(&pc_machine_type_##suffix); \
    331    } \
    332    type_init(pc_machine_init_##suffix)
    333
    334extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
    335#endif