cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

x86.h (4765B)

      1/*
      2 * Copyright (c) 2019 Red Hat, Inc.
      3 *
      4 * This program is free software; you can redistribute it and/or modify it
      5 * under the terms and conditions of the GNU General Public License,
      6 * version 2 or later, as published by the Free Software Foundation.
      7 *
      8 * This program is distributed in the hope it will be useful, but WITHOUT
      9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     11 * more details.
     12 *
     13 * You should have received a copy of the GNU General Public License along with
     14 * this program.  If not, see <http://www.gnu.org/licenses/>.
     15 */
     16
     17#ifndef HW_I386_X86_H
     18#define HW_I386_X86_H
     19
     20#include "qemu-common.h"
     21#include "exec/hwaddr.h"
     22#include "qemu/notify.h"
     23
     24#include "hw/i386/topology.h"
     25#include "hw/boards.h"
     26#include "hw/nmi.h"
     27#include "hw/isa/isa.h"
     28#include "hw/i386/ioapic.h"
     29#include "qom/object.h"
     30
     31struct X86MachineClass {
     32    /*< private >*/
     33    MachineClass parent;
     34
     35    /*< public >*/
     36
     37    /* TSC rate migration: */
     38    bool save_tsc_khz;
     39    /* Enables contiguous-apic-ID mode */
     40    bool compat_apic_id_mode;
     41};
     42
     43struct X86MachineState {
     44    /*< private >*/
     45    MachineState parent;
     46
     47    /*< public >*/
     48
     49    /* Pointers to devices and objects: */
     50    ISADevice *rtc;
     51    FWCfgState *fw_cfg;
     52    qemu_irq *gsi;
     53    DeviceState *ioapic2;
     54    GMappedFile *initrd_mapped_file;
     55    HotplugHandler *acpi_dev;
     56
     57    /* RAM information (sizes, addresses, configuration): */
     58    ram_addr_t below_4g_mem_size, above_4g_mem_size;
     59
     60    /* CPU and apic information: */
     61    bool apic_xrupt_override;
     62    unsigned pci_irq_mask;
     63    unsigned apic_id_limit;
     64    uint16_t boot_cpus;
     65    SgxEPCList *sgx_epc_list;
     66
     67    OnOffAuto smm;
     68    OnOffAuto acpi;
     69
     70    char *oem_id;
     71    char *oem_table_id;
     72    /*
     73     * Address space used by IOAPIC device. All IOAPIC interrupts
     74     * will be translated to MSI messages in the address space.
     75     */
     76    AddressSpace *ioapic_as;
     77
     78    /*
     79     * Ratelimit enforced on detected bus locks in guest.
     80     * The default value of the bus_lock_ratelimit is 0 per second,
     81     * which means no limitation on the guest's bus locks.
     82     */
     83    uint64_t bus_lock_ratelimit;
     84};
     85
     86#define X86_MACHINE_SMM              "smm"
     87#define X86_MACHINE_ACPI             "acpi"
     88#define X86_MACHINE_OEM_ID           "x-oem-id"
     89#define X86_MACHINE_OEM_TABLE_ID     "x-oem-table-id"
     90#define X86_MACHINE_BUS_LOCK_RATELIMIT  "bus-lock-ratelimit"
     91
     92#define TYPE_X86_MACHINE   MACHINE_TYPE_NAME("x86")
     93OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE)
     94
     95void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms);
     96
     97uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms,
     98                                    unsigned int cpu_index);
     99
    100void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp);
    101void x86_cpus_init(X86MachineState *pcms, int default_cpu_version);
    102CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms,
    103                                             unsigned cpu_index);
    104int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx);
    105const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms);
    106CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx);
    107void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count);
    108void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
    109                      DeviceState *dev, Error **errp);
    110void x86_cpu_plug(HotplugHandler *hotplug_dev,
    111                  DeviceState *dev, Error **errp);
    112void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev,
    113                               DeviceState *dev, Error **errp);
    114void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev,
    115                       DeviceState *dev, Error **errp);
    116
    117void x86_bios_rom_init(MachineState *ms, const char *default_firmware,
    118                       MemoryRegion *rom_memory, bool isapc_ram_fw);
    119
    120void x86_load_linux(X86MachineState *x86ms,
    121                    FWCfgState *fw_cfg,
    122                    int acpi_data_size,
    123                    bool pvh_enabled,
    124                    bool linuxboot_dma_enabled);
    125
    126bool x86_machine_is_smm_enabled(const X86MachineState *x86ms);
    127bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms);
    128
    129/* Global System Interrupts */
    130
    131#define GSI_NUM_PINS IOAPIC_NUM_PINS
    132#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
    133
    134typedef struct GSIState {
    135    qemu_irq i8259_irq[ISA_NUM_IRQS];
    136    qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
    137    qemu_irq ioapic2_irq[IOAPIC_NUM_PINS];
    138} GSIState;
    139
    140qemu_irq x86_allocate_cpu_irq(void);
    141void gsi_handler(void *opaque, int n, int level);
    142void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
    143DeviceState *ioapic_init_secondary(GSIState *gsi_state);
    144
    145#endif