cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

arm_gicv3_its_common.h (2927B)

      1/*
      2 * ITS support for ARM GICv3
      3 *
      4 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
      5 * Written by Pavel Fedin
      6 *
      7 * This program is free software; you can redistribute it and/or modify
      8 * it under the terms of the GNU General Public License as published by
      9 * the Free Software Foundation, either version 2 of the License, or
     10 * (at your option) any later version.
     11 *
     12 * This program is distributed in the hope that it will be useful,
     13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15 * GNU General Public License for more details.
     16 *
     17 * You should have received a copy of the GNU General Public License along
     18 * with this program; if not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21#ifndef QEMU_ARM_GICV3_ITS_COMMON_H
     22#define QEMU_ARM_GICV3_ITS_COMMON_H
     23
     24#include "hw/sysbus.h"
     25#include "hw/intc/arm_gicv3_common.h"
     26#include "qom/object.h"
     27
     28#define TYPE_ARM_GICV3_ITS "arm-gicv3-its"
     29
     30#define ITS_CONTROL_SIZE 0x10000
     31#define ITS_TRANS_SIZE   0x10000
     32#define ITS_SIZE         (ITS_CONTROL_SIZE + ITS_TRANS_SIZE)
     33
     34#define GITS_CTLR        0x0
     35#define GITS_IIDR        0x4
     36#define GITS_TYPER       0x8
     37#define GITS_CBASER      0x80
     38#define GITS_CWRITER     0x88
     39#define GITS_CREADR      0x90
     40#define GITS_BASER       0x100
     41
     42#define GITS_TRANSLATER  0x0040
     43
     44typedef struct {
     45    bool valid;
     46    bool indirect;
     47    uint16_t entry_sz;
     48    uint32_t page_sz;
     49    uint32_t max_entries;
     50    union {
     51        uint32_t max_devids;
     52        uint32_t max_collids;
     53    } maxids;
     54    uint64_t base_addr;
     55} TableDesc;
     56
     57typedef struct {
     58    bool valid;
     59    uint32_t max_entries;
     60    uint64_t base_addr;
     61} CmdQDesc;
     62
     63struct GICv3ITSState {
     64    SysBusDevice parent_obj;
     65
     66    MemoryRegion iomem_main;
     67    MemoryRegion iomem_its_cntrl;
     68    MemoryRegion iomem_its_translation;
     69
     70    GICv3State *gicv3;
     71
     72    int dev_fd; /* kvm device fd if backed by kvm vgic support */
     73    uint64_t gits_translater_gpa;
     74    bool translater_gpa_known;
     75
     76    /* Registers */
     77    uint32_t ctlr;
     78    uint32_t iidr;
     79    uint64_t typer;
     80    uint64_t cbaser;
     81    uint64_t cwriter;
     82    uint64_t creadr;
     83    uint64_t baser[8];
     84
     85    TableDesc  dt;
     86    TableDesc  ct;
     87    CmdQDesc   cq;
     88
     89    Error *migration_blocker;
     90};
     91
     92typedef struct GICv3ITSState GICv3ITSState;
     93
     94void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops,
     95                   const MemoryRegionOps *tops);
     96
     97#define TYPE_ARM_GICV3_ITS_COMMON "arm-gicv3-its-common"
     98typedef struct GICv3ITSCommonClass GICv3ITSCommonClass;
     99DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSCommonClass,
    100                     ARM_GICV3_ITS_COMMON, TYPE_ARM_GICV3_ITS_COMMON)
    101
    102struct GICv3ITSCommonClass {
    103    /*< private >*/
    104    SysBusDeviceClass parent_class;
    105    /*< public >*/
    106
    107    int (*send_msi)(GICv3ITSState *s, uint32_t data, uint16_t devid);
    108    void (*pre_save)(GICv3ITSState *s);
    109    void (*post_load)(GICv3ITSState *s);
    110};
    111
    112
    113#endif