cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

riscv_aclint.h (2461B)

      1/*
      2 * RISC-V ACLINT (Advanced Core Local Interruptor) interface
      3 *
      4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
      5 * Copyright (c) 2017 SiFive, Inc.
      6 * Copyright (c) 2021 Western Digital Corporation or its affiliates.
      7 *
      8 * This program is free software; you can redistribute it and/or modify it
      9 * under the terms and conditions of the GNU General Public License,
     10 * version 2 or later, as published by the Free Software Foundation.
     11 *
     12 * This program is distributed in the hope it will be useful, but WITHOUT
     13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     15 * more details.
     16 *
     17 * You should have received a copy of the GNU General Public License along with
     18 * this program.  If not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21#ifndef HW_RISCV_ACLINT_H
     22#define HW_RISCV_ACLINT_H
     23
     24#include "hw/sysbus.h"
     25
     26#define TYPE_RISCV_ACLINT_MTIMER "riscv.aclint.mtimer"
     27
     28#define RISCV_ACLINT_MTIMER(obj) \
     29    OBJECT_CHECK(RISCVAclintMTimerState, (obj), TYPE_RISCV_ACLINT_MTIMER)
     30
     31typedef struct RISCVAclintMTimerState {
     32    /*< private >*/
     33    SysBusDevice parent_obj;
     34
     35    /*< public >*/
     36    MemoryRegion mmio;
     37    uint32_t hartid_base;
     38    uint32_t num_harts;
     39    uint32_t timecmp_base;
     40    uint32_t time_base;
     41    uint32_t aperture_size;
     42    uint32_t timebase_freq;
     43    qemu_irq *timer_irqs;
     44} RISCVAclintMTimerState;
     45
     46DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
     47    uint32_t hartid_base, uint32_t num_harts,
     48    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
     49    bool provide_rdtime);
     50
     51#define TYPE_RISCV_ACLINT_SWI "riscv.aclint.swi"
     52
     53#define RISCV_ACLINT_SWI(obj) \
     54    OBJECT_CHECK(RISCVAclintSwiState, (obj), TYPE_RISCV_ACLINT_SWI)
     55
     56typedef struct RISCVAclintSwiState {
     57    /*< private >*/
     58    SysBusDevice parent_obj;
     59
     60    /*< public >*/
     61    MemoryRegion mmio;
     62    uint32_t hartid_base;
     63    uint32_t num_harts;
     64    uint32_t sswi;
     65    qemu_irq *soft_irqs;
     66} RISCVAclintSwiState;
     67
     68DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
     69    uint32_t num_harts, bool sswi);
     70
     71enum {
     72    RISCV_ACLINT_DEFAULT_MTIMECMP      = 0x0,
     73    RISCV_ACLINT_DEFAULT_MTIME         = 0x7ff8,
     74    RISCV_ACLINT_DEFAULT_MTIMER_SIZE   = 0x8000,
     75    RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ = 10000000,
     76    RISCV_ACLINT_MAX_HARTS             = 4095,
     77    RISCV_ACLINT_SWI_SIZE              = 0x4000
     78};
     79
     80#endif