cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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pc87312.h (1730B)

      1/*
      2 * QEMU National Semiconductor PC87312 (Super I/O)
      3 *
      4 * Copyright (c) 2010-2012 Herve Poussineau
      5 * Copyright (c) 2011-2012 Andreas Färber
      6 *
      7 * Permission is hereby granted, free of charge, to any person obtaining a copy
      8 * of this software and associated documentation files (the "Software"), to deal
      9 * in the Software without restriction, including without limitation the rights
     10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     11 * copies of the Software, and to permit persons to whom the Software is
     12 * furnished to do so, subject to the following conditions:
     13 *
     14 * The above copyright notice and this permission notice shall be included in
     15 * all copies or substantial portions of the Software.
     16 *
     17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     23 * THE SOFTWARE.
     24 */
     25#ifndef QEMU_PC87312_H
     26#define QEMU_PC87312_H
     27
     28#include "hw/isa/superio.h"
     29#include "qom/object.h"
     30
     31
     32#define TYPE_PC87312 "pc87312"
     33OBJECT_DECLARE_SIMPLE_TYPE(PC87312State, PC87312)
     34
     35struct PC87312State {
     36    /*< private >*/
     37    ISASuperIODevice parent_dev;
     38    /*< public >*/
     39
     40    uint16_t iobase;
     41    uint8_t config; /* initial configuration */
     42
     43    struct {
     44        ISADevice *dev;
     45    } ide;
     46
     47    MemoryRegion io;
     48
     49    uint8_t read_id_step;
     50    uint8_t selected_index;
     51
     52    uint8_t regs[3];
     53};
     54
     55
     56#endif