cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

cps.h (1434B)

      1/*
      2 * Coherent Processing System emulation.
      3 *
      4 * Copyright (c) 2016 Imagination Technologies
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef MIPS_CPS_H
     21#define MIPS_CPS_H
     22
     23#include "hw/sysbus.h"
     24#include "hw/clock.h"
     25#include "hw/misc/mips_cmgcr.h"
     26#include "hw/intc/mips_gic.h"
     27#include "hw/misc/mips_cpc.h"
     28#include "hw/misc/mips_itu.h"
     29#include "target/mips/cpu.h"
     30#include "qom/object.h"
     31
     32#define TYPE_MIPS_CPS "mips-cps"
     33OBJECT_DECLARE_SIMPLE_TYPE(MIPSCPSState, MIPS_CPS)
     34
     35struct MIPSCPSState {
     36    SysBusDevice parent_obj;
     37
     38    uint32_t num_vp;
     39    uint32_t num_irq;
     40    char *cpu_type;
     41
     42    MemoryRegion container;
     43    MIPSGCRState gcr;
     44    MIPSGICState gic;
     45    MIPSCPCState cpc;
     46    MIPSITUState itu;
     47    Clock *clock;
     48};
     49
     50qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
     51
     52#endif