cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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allwinner-h3-ccu.h (1641B)

      1/*
      2 * Allwinner H3 Clock Control Unit emulation
      3 *
      4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
      5 *
      6 * This program is free software: you can redistribute it and/or modify
      7 * it under the terms of the GNU General Public License as published by
      8 * the Free Software Foundation, either version 2 of the License, or
      9 * (at your option) any later version.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef HW_MISC_ALLWINNER_H3_CCU_H
     21#define HW_MISC_ALLWINNER_H3_CCU_H
     22
     23#include "qom/object.h"
     24#include "hw/sysbus.h"
     25
     26/**
     27 * @name Constants
     28 * @{
     29 */
     30
     31/** Size of register I/O address space used by CCU device */
     32#define AW_H3_CCU_IOSIZE        (0x400)
     33
     34/** Total number of known registers */
     35#define AW_H3_CCU_REGS_NUM      (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
     36
     37/** @} */
     38
     39/**
     40 * @name Object model
     41 * @{
     42 */
     43
     44#define TYPE_AW_H3_CCU    "allwinner-h3-ccu"
     45OBJECT_DECLARE_SIMPLE_TYPE(AwH3ClockCtlState, AW_H3_CCU)
     46
     47/** @} */
     48
     49/**
     50 * Allwinner H3 CCU object instance state.
     51 */
     52struct AwH3ClockCtlState {
     53    /*< private >*/
     54    SysBusDevice parent_obj;
     55    /*< public >*/
     56
     57    /** Maps I/O registers in physical memory */
     58    MemoryRegion iomem;
     59
     60    /** Array of hardware registers */
     61    uint32_t regs[AW_H3_CCU_REGS_NUM];
     62
     63};
     64
     65#endif /* HW_MISC_ALLWINNER_H3_CCU_H */