cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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allwinner-h3-sysctrl.h (1739B)

      1/*
      2 * Allwinner H3 System Control emulation
      3 *
      4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
      5 *
      6 * This program is free software: you can redistribute it and/or modify
      7 * it under the terms of the GNU General Public License as published by
      8 * the Free Software Foundation, either version 2 of the License, or
      9 * (at your option) any later version.
     10 *
     11 * This program is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14 * GNU General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU General Public License
     17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
     21#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
     22
     23#include "qom/object.h"
     24#include "hw/sysbus.h"
     25
     26/**
     27 * @name Constants
     28 * @{
     29 */
     30
     31/** Highest register address used by System Control device */
     32#define AW_H3_SYSCTRL_REGS_MAXADDR   (0x30)
     33
     34/** Total number of known registers */
     35#define AW_H3_SYSCTRL_REGS_NUM       ((AW_H3_SYSCTRL_REGS_MAXADDR / \
     36                                      sizeof(uint32_t)) + 1)
     37
     38/** @} */
     39
     40/**
     41 * @name Object model
     42 * @{
     43 */
     44
     45#define TYPE_AW_H3_SYSCTRL    "allwinner-h3-sysctrl"
     46OBJECT_DECLARE_SIMPLE_TYPE(AwH3SysCtrlState, AW_H3_SYSCTRL)
     47
     48/** @} */
     49
     50/**
     51 * Allwinner H3 System Control object instance state
     52 */
     53struct AwH3SysCtrlState {
     54    /*< private >*/
     55    SysBusDevice parent_obj;
     56    /*< public >*/
     57
     58    /** Maps I/O registers in physical memory */
     59    MemoryRegion iomem;
     60
     61    /** Array of hardware registers */
     62    uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
     63
     64};
     65
     66#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */