cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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armsse-mhu.h (1055B)

      1/*
      2 * ARM SSE-200 Message Handling Unit (MHU)
      3 *
      4 * Copyright (c) 2019 Linaro Limited
      5 * Written by Peter Maydell
      6 *
      7 *  This program is free software; you can redistribute it and/or modify
      8 *  it under the terms of the GNU General Public License version 2 or
      9 *  (at your option) any later version.
     10 */
     11
     12/*
     13 * This is a model of the Message Handling Unit (MHU) which is part of the
     14 * Arm SSE-200 and documented in
     15 * https://developer.arm.com/documentation/101104/latest/
     16 *
     17 * QEMU interface:
     18 *  + sysbus MMIO region 0: the system information register bank
     19 *  + sysbus IRQ 0: interrupt for CPU 0
     20 *  + sysbus IRQ 1: interrupt for CPU 1
     21 */
     22
     23#ifndef HW_MISC_ARMSSE_MHU_H
     24#define HW_MISC_ARMSSE_MHU_H
     25
     26#include "hw/sysbus.h"
     27#include "qom/object.h"
     28
     29#define TYPE_ARMSSE_MHU "armsse-mhu"
     30OBJECT_DECLARE_SIMPLE_TYPE(ARMSSEMHU, ARMSSE_MHU)
     31
     32struct ARMSSEMHU {
     33    /*< private >*/
     34    SysBusDevice parent_obj;
     35
     36    /*< public >*/
     37    MemoryRegion iomem;
     38    qemu_irq cpu0irq;
     39    qemu_irq cpu1irq;
     40
     41    uint32_t cpu0intr;
     42    uint32_t cpu1intr;
     43};
     44
     45#endif