cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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armv7m_ras.h (867B)

      1/*
      2 * Arm M-profile RAS (Reliability, Availability and Serviceability) block
      3 *
      4 * Copyright (c) 2021 Linaro Limited
      5 *
      6 *  This program is free software; you can redistribute it and/or modify
      7 *  it under the terms of the GNU General Public License version 2 or
      8 *  (at your option) any later version.
      9 */
     10
     11/*
     12 * This is a model of the RAS register block of an M-profile CPU
     13 * (the registers starting at 0xE0005000 with ERRFRn).
     14 *
     15 * QEMU interface:
     16 *  + sysbus MMIO region 0: the register bank
     17 *
     18 * The QEMU implementation currently provides "minimal RAS" only.
     19 */
     20
     21#ifndef HW_MISC_ARMV7M_RAS_H
     22#define HW_MISC_ARMV7M_RAS_H
     23
     24#include "hw/sysbus.h"
     25
     26#define TYPE_ARMV7M_RAS "armv7m-ras"
     27OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MRAS, ARMV7M_RAS)
     28
     29struct ARMv7MRAS {
     30    /*< private >*/
     31    SysBusDevice parent_obj;
     32
     33    /*< public >*/
     34    MemoryRegion iomem;
     35};
     36
     37#endif