cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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imx25_ccm.h (2230B)

      1/*
      2 * IMX25 Clock Control Module
      3 *
      4 * Copyright (C) 2012 NICTA
      5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
      6 *
      7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
      8 * See the COPYING file in the top-level directory.
      9 */
     10
     11#ifndef IMX25_CCM_H
     12#define IMX25_CCM_H
     13
     14#include "hw/misc/imx_ccm.h"
     15#include "qom/object.h"
     16
     17#define IMX25_CCM_MPCTL_REG  0
     18#define IMX25_CCM_UPCTL_REG  1
     19#define IMX25_CCM_CCTL_REG   2
     20#define IMX25_CCM_CGCR0_REG  3
     21#define IMX25_CCM_CGCR1_REG  4
     22#define IMX25_CCM_CGCR2_REG  5
     23#define IMX25_CCM_PCDR0_REG  6
     24#define IMX25_CCM_PCDR1_REG  7
     25#define IMX25_CCM_PCDR2_REG  8
     26#define IMX25_CCM_PCDR3_REG  9
     27#define IMX25_CCM_RCSR_REG   10
     28#define IMX25_CCM_CRDR_REG   11
     29#define IMX25_CCM_DCVR0_REG  12
     30#define IMX25_CCM_DCVR1_REG  13
     31#define IMX25_CCM_DCVR2_REG  14
     32#define IMX25_CCM_DCVR3_REG  15
     33#define IMX25_CCM_LTR0_REG   16
     34#define IMX25_CCM_LTR1_REG   17
     35#define IMX25_CCM_LTR2_REG   18
     36#define IMX25_CCM_LTR3_REG   19
     37#define IMX25_CCM_LTBR0_REG  20
     38#define IMX25_CCM_LTBR1_REG  21
     39#define IMX25_CCM_PMCR0_REG  22
     40#define IMX25_CCM_PMCR1_REG  23
     41#define IMX25_CCM_PMCR2_REG  24
     42#define IMX25_CCM_MCR_REG    25
     43#define IMX25_CCM_LPIMR0_REG 26
     44#define IMX25_CCM_LPIMR1_REG 27
     45#define IMX25_CCM_MAX_REG    28
     46
     47/* CCTL */
     48#define CCTL_ARM_CLK_DIV_SHIFT (30)
     49#define CCTL_ARM_CLK_DIV_MASK  (0x3)
     50#define CCTL_AHB_CLK_DIV_SHIFT (28)
     51#define CCTL_AHB_CLK_DIV_MASK  (0x3)
     52#define CCTL_MPLL_BYPASS_SHIFT (22)
     53#define CCTL_MPLL_BYPASS_MASK  (0x1)
     54#define CCTL_USB_DIV_SHIFT     (16)
     55#define CCTL_USB_DIV_MASK      (0x3F)
     56#define CCTL_ARM_SRC_SHIFT     (13)
     57#define CCTL_ARM_SRC_MASK      (0x1)
     58#define CCTL_UPLL_DIS_SHIFT    (23)
     59#define CCTL_UPLL_DIS_MASK     (0x1)
     60
     61#define EXTRACT(value, name) (((value) >> CCTL_##name##_SHIFT) \
     62                              & CCTL_##name##_MASK)
     63#define INSERT(value, name) (((value) & CCTL_##name##_MASK) << \
     64                             CCTL_##name##_SHIFT)
     65
     66#define TYPE_IMX25_CCM "imx25.ccm"
     67OBJECT_DECLARE_SIMPLE_TYPE(IMX25CCMState, IMX25_CCM)
     68
     69struct IMX25CCMState {
     70    /* <private> */
     71    IMXCCMState parent_obj;
     72
     73    /* <public> */
     74    MemoryRegion iomem;
     75
     76    uint32_t reg[IMX25_CCM_MAX_REG];
     77
     78};
     79
     80#endif /* IMX25_CCM_H */