cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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mips_cmgcr.h (2628B)

      1/*
      2 * This file is subject to the terms and conditions of the GNU General Public
      3 * License.  See the file "COPYING" in the main directory of this archive
      4 * for more details.
      5 *
      6 * Copyright (C) 2015 Imagination Technologies
      7 *
      8 */
      9
     10#ifndef MIPS_CMGCR_H
     11#define MIPS_CMGCR_H
     12
     13#include "hw/sysbus.h"
     14#include "qom/object.h"
     15
     16#define TYPE_MIPS_GCR "mips-gcr"
     17OBJECT_DECLARE_SIMPLE_TYPE(MIPSGCRState, MIPS_GCR)
     18
     19#define GCR_BASE_ADDR           0x1fbf8000ULL
     20#define GCR_ADDRSPACE_SZ        0x8000
     21
     22/* Offsets to register blocks */
     23#define MIPS_GCB_OFS        0x0000 /* Global Control Block */
     24#define MIPS_CLCB_OFS       0x2000 /* Core Local Control Block */
     25#define MIPS_COCB_OFS       0x4000 /* Core Other Control Block */
     26#define MIPS_GDB_OFS        0x6000 /* Global Debug Block */
     27
     28/* Global Control Block Register Map */
     29#define GCR_CONFIG_OFS      0x0000
     30#define GCR_BASE_OFS        0x0008
     31#define GCR_REV_OFS         0x0030
     32#define GCR_GIC_BASE_OFS    0x0080
     33#define GCR_CPC_BASE_OFS    0x0088
     34#define GCR_GIC_STATUS_OFS  0x00D0
     35#define GCR_CPC_STATUS_OFS  0x00F0
     36#define GCR_L2_CONFIG_OFS   0x0130
     37
     38/* Core Local and Core Other Block Register Map */
     39#define GCR_CL_CONFIG_OFS   0x0010
     40#define GCR_CL_OTHER_OFS    0x0018
     41#define GCR_CL_RESETBASE_OFS 0x0020
     42
     43/* GCR_L2_CONFIG register fields */
     44#define GCR_L2_CONFIG_BYPASS_SHF    20
     45#define GCR_L2_CONFIG_BYPASS_MSK    ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
     46
     47/* GCR_BASE register fields */
     48#define GCR_BASE_GCRBASE_MSK     0xffffffff8000ULL
     49
     50/* GCR_GIC_BASE register fields */
     51#define GCR_GIC_BASE_GICEN_MSK   1
     52#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
     53#define GCR_GIC_BASE_MSK (GCR_GIC_BASE_GICEN_MSK | GCR_GIC_BASE_GICBASE_MSK)
     54
     55/* GCR_CPC_BASE register fields */
     56#define GCR_CPC_BASE_CPCEN_MSK   1
     57#define GCR_CPC_BASE_CPCBASE_MSK 0xFFFFFFFF8000ULL
     58#define GCR_CPC_BASE_MSK (GCR_CPC_BASE_CPCEN_MSK | GCR_CPC_BASE_CPCBASE_MSK)
     59
     60/* GCR_CL_OTHER_OFS register fields */
     61#define GCR_CL_OTHER_VPOTHER_MSK 0x7
     62#define GCR_CL_OTHER_MSK GCR_CL_OTHER_VPOTHER_MSK
     63
     64/* GCR_CL_RESETBASE_OFS register fields */
     65#define GCR_CL_RESET_BASE_RESETBASE_MSK 0xFFFFF000U
     66#define GCR_CL_RESET_BASE_MSK GCR_CL_RESET_BASE_RESETBASE_MSK
     67
     68typedef struct MIPSGCRVPState MIPSGCRVPState;
     69struct MIPSGCRVPState {
     70    uint32_t other;
     71    uint64_t reset_base;
     72};
     73
     74struct MIPSGCRState {
     75    SysBusDevice parent_obj;
     76
     77    int32_t gcr_rev;
     78    int32_t num_vps;
     79    hwaddr gcr_base;
     80    MemoryRegion iomem;
     81    MemoryRegion *cpc_mr;
     82    MemoryRegion *gic_mr;
     83
     84    uint64_t cpc_base;
     85    uint64_t gic_base;
     86
     87    /* VP Local/Other Registers */
     88    MIPSGCRVPState *vps;
     89};
     90
     91#endif /* MIPS_CMGCR_H */