cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

mips_itu.h (2289B)

      1/*
      2 * Inter-Thread Communication Unit emulation.
      3 *
      4 * Copyright (c) 2016 Imagination Technologies
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef MIPS_ITU_H
     21#define MIPS_ITU_H
     22
     23#include "hw/sysbus.h"
     24#include "qom/object.h"
     25
     26#define TYPE_MIPS_ITU "mips-itu"
     27OBJECT_DECLARE_SIMPLE_TYPE(MIPSITUState, MIPS_ITU)
     28
     29#define ITC_CELL_DEPTH_SHIFT 2
     30#define ITC_CELL_DEPTH (1u << ITC_CELL_DEPTH_SHIFT)
     31
     32typedef struct ITCStorageCell {
     33    struct {
     34        uint8_t FIFODepth; /* Log2 of the cell depth */
     35        uint8_t FIFOPtr; /* Number of elements in a FIFO cell */
     36        uint8_t FIFO; /* 1 - FIFO cell, 0 - Semaphore cell */
     37        uint8_t T; /* Trap Bit */
     38        uint8_t F; /* Full Bit */
     39        uint8_t E; /* Empty Bit */
     40    } tag;
     41
     42    /* Index of the oldest element in the queue */
     43    uint8_t fifo_out;
     44
     45    /* Circular buffer for FIFO. Semaphore cells use index 0 only */
     46    uint64_t data[ITC_CELL_DEPTH];
     47
     48    /* Bitmap tracking blocked threads on the cell.
     49       TODO: support >64 threads ? */
     50    uint64_t blocked_threads;
     51} ITCStorageCell;
     52
     53#define ITC_ADDRESSMAP_NUM 2
     54
     55struct MIPSITUState {
     56    /*< private >*/
     57    SysBusDevice parent_obj;
     58    /*< public >*/
     59
     60    int32_t num_fifo;
     61    int32_t num_semaphores;
     62
     63    /* ITC Storage */
     64    ITCStorageCell *cell;
     65    MemoryRegion storage_io;
     66
     67    /* ITC Configuration Tags */
     68    uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
     69    MemoryRegion tag_io;
     70
     71    /* ITU Control Register */
     72    uint64_t icr0;
     73
     74    /* SAAR */
     75    bool saar_present;
     76    void *saar;
     77
     78};
     79
     80/* Get ITC Configuration Tag memory region. */
     81MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu);
     82
     83#endif /* MIPS_ITU_H */