cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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xlnx-versal-xramc.h (2726B)

      1/*
      2 * QEMU model of the Xilinx XRAM Controller.
      3 *
      4 * Copyright (c) 2021 Xilinx Inc.
      5 * SPDX-License-Identifier: GPL-2.0-or-later
      6 * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
      7 */
      8
      9#ifndef XLNX_VERSAL_XRAMC_H
     10#define XLNX_VERSAL_XRAMC_H
     11
     12#include "hw/sysbus.h"
     13#include "hw/register.h"
     14
     15#define TYPE_XLNX_XRAM_CTRL "xlnx.versal-xramc"
     16
     17#define XLNX_XRAM_CTRL(obj) \
     18     OBJECT_CHECK(XlnxXramCtrl, (obj), TYPE_XLNX_XRAM_CTRL)
     19
     20REG32(XRAM_ERR_CTRL, 0x0)
     21    FIELD(XRAM_ERR_CTRL, UE_RES, 3, 1)
     22    FIELD(XRAM_ERR_CTRL, PWR_ERR_RES, 2, 1)
     23    FIELD(XRAM_ERR_CTRL, PZ_ERR_RES, 1, 1)
     24    FIELD(XRAM_ERR_CTRL, APB_ERR_RES, 0, 1)
     25REG32(XRAM_ISR, 0x4)
     26    FIELD(XRAM_ISR, INV_APB, 0, 1)
     27REG32(XRAM_IMR, 0x8)
     28    FIELD(XRAM_IMR, INV_APB, 0, 1)
     29REG32(XRAM_IEN, 0xc)
     30    FIELD(XRAM_IEN, INV_APB, 0, 1)
     31REG32(XRAM_IDS, 0x10)
     32    FIELD(XRAM_IDS, INV_APB, 0, 1)
     33REG32(XRAM_ECC_CNTL, 0x14)
     34    FIELD(XRAM_ECC_CNTL, FI_MODE, 2, 1)
     35    FIELD(XRAM_ECC_CNTL, DET_ONLY, 1, 1)
     36    FIELD(XRAM_ECC_CNTL, ECC_ON_OFF, 0, 1)
     37REG32(XRAM_CLR_EXE, 0x18)
     38    FIELD(XRAM_CLR_EXE, MON_7, 7, 1)
     39    FIELD(XRAM_CLR_EXE, MON_6, 6, 1)
     40    FIELD(XRAM_CLR_EXE, MON_5, 5, 1)
     41    FIELD(XRAM_CLR_EXE, MON_4, 4, 1)
     42    FIELD(XRAM_CLR_EXE, MON_3, 3, 1)
     43    FIELD(XRAM_CLR_EXE, MON_2, 2, 1)
     44    FIELD(XRAM_CLR_EXE, MON_1, 1, 1)
     45    FIELD(XRAM_CLR_EXE, MON_0, 0, 1)
     46REG32(XRAM_CE_FFA, 0x1c)
     47    FIELD(XRAM_CE_FFA, ADDR, 0, 20)
     48REG32(XRAM_CE_FFD0, 0x20)
     49REG32(XRAM_CE_FFD1, 0x24)
     50REG32(XRAM_CE_FFD2, 0x28)
     51REG32(XRAM_CE_FFD3, 0x2c)
     52REG32(XRAM_CE_FFE, 0x30)
     53    FIELD(XRAM_CE_FFE, SYNDROME, 0, 16)
     54REG32(XRAM_UE_FFA, 0x34)
     55    FIELD(XRAM_UE_FFA, ADDR, 0, 20)
     56REG32(XRAM_UE_FFD0, 0x38)
     57REG32(XRAM_UE_FFD1, 0x3c)
     58REG32(XRAM_UE_FFD2, 0x40)
     59REG32(XRAM_UE_FFD3, 0x44)
     60REG32(XRAM_UE_FFE, 0x48)
     61    FIELD(XRAM_UE_FFE, SYNDROME, 0, 16)
     62REG32(XRAM_FI_D0, 0x4c)
     63REG32(XRAM_FI_D1, 0x50)
     64REG32(XRAM_FI_D2, 0x54)
     65REG32(XRAM_FI_D3, 0x58)
     66REG32(XRAM_FI_SY, 0x5c)
     67    FIELD(XRAM_FI_SY, DATA, 0, 16)
     68REG32(XRAM_RMW_UE_FFA, 0x70)
     69    FIELD(XRAM_RMW_UE_FFA, ADDR, 0, 20)
     70REG32(XRAM_FI_CNTR, 0x74)
     71    FIELD(XRAM_FI_CNTR, COUNT, 0, 24)
     72REG32(XRAM_IMP, 0x80)
     73    FIELD(XRAM_IMP, SIZE, 0, 4)
     74REG32(XRAM_PRDY_DBG, 0x84)
     75    FIELD(XRAM_PRDY_DBG, ISLAND3, 12, 4)
     76    FIELD(XRAM_PRDY_DBG, ISLAND2, 8, 4)
     77    FIELD(XRAM_PRDY_DBG, ISLAND1, 4, 4)
     78    FIELD(XRAM_PRDY_DBG, ISLAND0, 0, 4)
     79REG32(XRAM_SAFETY_CHK, 0xff8)
     80
     81#define XRAM_CTRL_R_MAX (R_XRAM_SAFETY_CHK + 1)
     82
     83typedef struct XlnxXramCtrl {
     84    SysBusDevice parent_obj;
     85    MemoryRegion ram;
     86    qemu_irq irq;
     87
     88    struct {
     89        uint64_t size;
     90        unsigned int encoded_size;
     91    } cfg;
     92
     93    RegisterInfoArray *reg_array;
     94    uint32_t regs[XRAM_CTRL_R_MAX];
     95    RegisterInfo regs_info[XRAM_CTRL_R_MAX];
     96} XlnxXramCtrl;
     97#endif