cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

ftgmac100.h (1652B)

      1/*
      2 * Faraday FTGMAC100 Gigabit Ethernet
      3 *
      4 * Copyright (C) 2016-2017, IBM Corporation.
      5 *
      6 * This code is licensed under the GPL version 2 or later. See the
      7 * COPYING file in the top-level directory.
      8 */
      9
     10#ifndef FTGMAC100_H
     11#define FTGMAC100_H
     12#include "qom/object.h"
     13
     14#define TYPE_FTGMAC100 "ftgmac100"
     15OBJECT_DECLARE_SIMPLE_TYPE(FTGMAC100State, FTGMAC100)
     16
     17#include "hw/sysbus.h"
     18#include "net/net.h"
     19
     20/*
     21 * Max frame size for the receiving buffer
     22 */
     23#define FTGMAC100_MAX_FRAME_SIZE    9220
     24
     25struct FTGMAC100State {
     26    /*< private >*/
     27    SysBusDevice parent_obj;
     28
     29    /*< public >*/
     30    NICState *nic;
     31    NICConf conf;
     32    qemu_irq irq;
     33    MemoryRegion iomem;
     34
     35    uint8_t frame[FTGMAC100_MAX_FRAME_SIZE];
     36
     37    uint32_t irq_state;
     38    uint32_t isr;
     39    uint32_t ier;
     40    uint32_t rx_enabled;
     41    uint32_t rx_ring;
     42    uint32_t rx_descriptor;
     43    uint32_t tx_ring;
     44    uint32_t tx_descriptor;
     45    uint32_t math[2];
     46    uint32_t rbsr;
     47    uint32_t itc;
     48    uint32_t aptcr;
     49    uint32_t dblac;
     50    uint32_t revr;
     51    uint32_t fear1;
     52    uint32_t tpafcr;
     53    uint32_t maccr;
     54    uint32_t phycr;
     55    uint32_t phydata;
     56    uint32_t fcr;
     57
     58
     59    uint32_t phy_status;
     60    uint32_t phy_control;
     61    uint32_t phy_advertise;
     62    uint32_t phy_int;
     63    uint32_t phy_int_mask;
     64
     65    bool aspeed;
     66    uint32_t txdes0_edotr;
     67    uint32_t rxdes0_edorr;
     68};
     69
     70#define TYPE_ASPEED_MII "aspeed-mmi"
     71OBJECT_DECLARE_SIMPLE_TYPE(AspeedMiiState, ASPEED_MII)
     72
     73/*
     74 * AST2600 MII controller
     75 */
     76struct AspeedMiiState {
     77    /*< private >*/
     78    SysBusDevice parent_obj;
     79
     80    FTGMAC100State *nic;
     81
     82    MemoryRegion iomem;
     83    uint32_t phycr;
     84    uint32_t phydata;
     85};
     86
     87#endif