cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

msf2-emac.h (1763B)

      1/*
      2 * QEMU model of the Smartfusion2 Ethernet MAC.
      3 *
      4 * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
      5 *
      6 * Permission is hereby granted, free of charge, to any person obtaining a copy
      7 * of this software and associated documentation files (the "Software"), to deal
      8 * in the Software without restriction, including without limitation the rights
      9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10 * copies of the Software, and to permit persons to whom the Software is
     11 * furnished to do so, subject to the following conditions:
     12 *
     13 * The above copyright notice and this permission notice shall be included in
     14 * all copies or substantial portions of the Software.
     15 *
     16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22 * THE SOFTWARE.
     23 */
     24
     25#include "hw/sysbus.h"
     26#include "exec/memory.h"
     27#include "net/net.h"
     28#include "net/eth.h"
     29#include "qom/object.h"
     30
     31#define TYPE_MSS_EMAC "msf2-emac"
     32OBJECT_DECLARE_SIMPLE_TYPE(MSF2EmacState, MSS_EMAC)
     33
     34#define R_MAX         (0x1a0 / 4)
     35#define PHY_MAX_REGS  32
     36
     37struct MSF2EmacState {
     38    SysBusDevice parent;
     39
     40    MemoryRegion mmio;
     41    MemoryRegion *dma_mr;
     42    AddressSpace dma_as;
     43
     44    qemu_irq irq;
     45    NICState *nic;
     46    NICConf conf;
     47
     48    uint8_t mac_addr[ETH_ALEN];
     49    uint32_t rx_desc;
     50    uint16_t phy_regs[PHY_MAX_REGS];
     51
     52    uint32_t regs[R_MAX];
     53};