cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

npcm7xx_otp.h (2621B)

      1/*
      2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
      3 *
      4 * Copyright 2020 Google LLC
      5 *
      6 * This program is free software; you can redistribute it and/or modify it
      7 * under the terms of the GNU General Public License as published by the
      8 * Free Software Foundation; either version 2 of the License, or
      9 * (at your option) any later version.
     10 *
     11 * This program is distributed in the hope that it will be useful, but WITHOUT
     12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
     14 * for more details.
     15 */
     16#ifndef NPCM7XX_OTP_H
     17#define NPCM7XX_OTP_H
     18
     19#include "exec/memory.h"
     20#include "hw/sysbus.h"
     21
     22/* Each OTP module holds 8192 bits of one-time programmable storage */
     23#define NPCM7XX_OTP_ARRAY_BITS (8192)
     24#define NPCM7XX_OTP_ARRAY_BYTES (NPCM7XX_OTP_ARRAY_BITS / BITS_PER_BYTE)
     25
     26/* Fuse array offsets */
     27#define NPCM7XX_FUSE_FUSTRAP (0)
     28#define NPCM7XX_FUSE_CP_FUSTRAP (12)
     29#define NPCM7XX_FUSE_DAC_CALIB (16)
     30#define NPCM7XX_FUSE_ADC_CALIB (24)
     31#define NPCM7XX_FUSE_DERIVATIVE (64)
     32#define NPCM7XX_FUSE_TEST_SIG (72)
     33#define NPCM7XX_FUSE_DIE_LOCATION (74)
     34#define NPCM7XX_FUSE_GP1 (80)
     35#define NPCM7XX_FUSE_GP2 (128)
     36
     37/*
     38 * Number of registers in our device state structure. Don't change this without
     39 * incrementing the version_id in the vmstate.
     40 */
     41#define NPCM7XX_OTP_NR_REGS (0x18 / sizeof(uint32_t))
     42
     43/**
     44 * struct NPCM7xxOTPState - Device state for one OTP module.
     45 * @parent: System bus device.
     46 * @mmio: Memory region through which registers are accessed.
     47 * @regs: Register contents.
     48 * @array: OTP storage array.
     49 */
     50typedef struct NPCM7xxOTPState {
     51    SysBusDevice parent;
     52
     53    MemoryRegion mmio;
     54    uint32_t regs[NPCM7XX_OTP_NR_REGS];
     55    uint8_t array[NPCM7XX_OTP_ARRAY_BYTES];
     56} NPCM7xxOTPState;
     57
     58#define TYPE_NPCM7XX_OTP "npcm7xx-otp"
     59#define NPCM7XX_OTP(obj) OBJECT_CHECK(NPCM7xxOTPState, (obj), TYPE_NPCM7XX_OTP)
     60
     61#define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
     62#define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
     63
     64typedef struct NPCM7xxOTPClass NPCM7xxOTPClass;
     65
     66/**
     67 * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
     68 * @s: OTP module.
     69 * @data: Data to be encoded and written.
     70 * @offset: Offset of first byte to be written in the OTP array.
     71 * @len: Number of bytes before ECC encoding.
     72 *
     73 * Each nibble of data is encoded into a byte, so the number of bytes written
     74 * to the array will be @len * 2.
     75 */
     76extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data,
     77                                    unsigned int offset, unsigned int len);
     78
     79#endif /* NPCM7XX_OTP_H */