cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

sabre.h (1244B)

      1#ifndef HW_PCI_HOST_SABRE_H
      2#define HW_PCI_HOST_SABRE_H
      3
      4#include "hw/pci/pci.h"
      5#include "hw/pci/pci_host.h"
      6#include "hw/sparc/sun4u_iommu.h"
      7#include "qom/object.h"
      8
      9#define MAX_IVEC 0x40
     10
     11/* OBIO IVEC IRQs */
     12#define OBIO_HDD_IRQ         0x20
     13#define OBIO_NIC_IRQ         0x21
     14#define OBIO_LPT_IRQ         0x22
     15#define OBIO_FDD_IRQ         0x27
     16#define OBIO_KBD_IRQ         0x29
     17#define OBIO_MSE_IRQ         0x2a
     18#define OBIO_SER_IRQ         0x2b
     19
     20struct SabrePCIState {
     21    PCIDevice parent_obj;
     22};
     23
     24#define TYPE_SABRE_PCI_DEVICE "sabre-pci"
     25OBJECT_DECLARE_SIMPLE_TYPE(SabrePCIState, SABRE_PCI_DEVICE)
     26
     27struct SabreState {
     28    PCIHostState parent_obj;
     29
     30    hwaddr special_base;
     31    hwaddr mem_base;
     32    MemoryRegion sabre_config;
     33    MemoryRegion pci_config;
     34    MemoryRegion pci_mmio;
     35    MemoryRegion pci_ioport;
     36    uint64_t pci_irq_in;
     37    IOMMUState *iommu;
     38    PCIBridge *bridgeA;
     39    PCIBridge *bridgeB;
     40    uint32_t pci_control[16];
     41    uint32_t pci_irq_map[8];
     42    uint32_t pci_err_irq_map[4];
     43    uint32_t obio_irq_map[32];
     44    qemu_irq ivec_irqs[MAX_IVEC];
     45    unsigned int irq_request;
     46    uint32_t reset_control;
     47    unsigned int nr_resets;
     48};
     49
     50#define TYPE_SABRE "sabre"
     51OBJECT_DECLARE_SIMPLE_TYPE(SabreState, SABRE)
     52
     53#endif