cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

pcie_port.h (2643B)

      1/*
      2 * pcie_port.h
      3 *
      4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
      5 *                    VA Linux Systems Japan K.K.
      6 *
      7 * This program is free software; you can redistribute it and/or modify
      8 * it under the terms of the GNU General Public License as published by
      9 * the Free Software Foundation; either version 2 of the License, or
     10 * (at your option) any later version.
     11 *
     12 * This program is distributed in the hope that it will be useful,
     13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15 * GNU General Public License for more details.
     16 *
     17 * You should have received a copy of the GNU General Public License along
     18 * with this program; if not, see <http://www.gnu.org/licenses/>.
     19 */
     20
     21#ifndef QEMU_PCIE_PORT_H
     22#define QEMU_PCIE_PORT_H
     23
     24#include "hw/pci/pci_bridge.h"
     25#include "hw/pci/pci_bus.h"
     26#include "qom/object.h"
     27
     28#define TYPE_PCIE_PORT "pcie-port"
     29OBJECT_DECLARE_SIMPLE_TYPE(PCIEPort, PCIE_PORT)
     30
     31struct PCIEPort {
     32    /*< private >*/
     33    PCIBridge   parent_obj;
     34    /*< public >*/
     35
     36    /* pci express switch port */
     37    uint8_t     port;
     38};
     39
     40void pcie_port_init_reg(PCIDevice *d);
     41
     42#define TYPE_PCIE_SLOT "pcie-slot"
     43OBJECT_DECLARE_SIMPLE_TYPE(PCIESlot, PCIE_SLOT)
     44
     45struct PCIESlot {
     46    /*< private >*/
     47    PCIEPort    parent_obj;
     48    /*< public >*/
     49
     50    /* pci express switch port with slot */
     51    uint8_t     chassis;
     52    uint16_t    slot;
     53
     54    PCIExpLinkSpeed speed;
     55    PCIExpLinkWidth width;
     56
     57    /* Disable ACS (really for a pcie_root_port) */
     58    bool        disable_acs;
     59
     60    /* Indicates whether any type of hot-plug is allowed on the slot */
     61    bool        hotplug;
     62
     63    bool        native_hotplug;
     64
     65    QLIST_ENTRY(PCIESlot) next;
     66};
     67
     68void pcie_chassis_create(uint8_t chassis_number);
     69PCIESlot *pcie_chassis_find_slot(uint8_t chassis, uint16_t slot);
     70int pcie_chassis_add_slot(struct PCIESlot *slot);
     71void pcie_chassis_del_slot(PCIESlot *s);
     72
     73#define TYPE_PCIE_ROOT_PORT         "pcie-root-port-base"
     74typedef struct PCIERootPortClass PCIERootPortClass;
     75DECLARE_CLASS_CHECKERS(PCIERootPortClass, PCIE_ROOT_PORT,
     76                       TYPE_PCIE_ROOT_PORT)
     77
     78struct PCIERootPortClass {
     79    PCIDeviceClass parent_class;
     80    DeviceRealize parent_realize;
     81    DeviceReset parent_reset;
     82
     83    uint8_t (*aer_vector)(const PCIDevice *dev);
     84    int (*interrupts_init)(PCIDevice *dev, Error **errp);
     85    void (*interrupts_uninit)(PCIDevice *dev);
     86
     87    int exp_offset;
     88    int aer_offset;
     89    int ssvid_offset;
     90    int acs_offset;    /* If nonzero, optional ACS capability offset */
     91    int ssid;
     92};
     93
     94#endif /* QEMU_PCIE_PORT_H */