cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

pnv.h (10235B)


      1/*
      2 * QEMU PowerPC PowerNV various definitions
      3 *
      4 * Copyright (c) 2014-2016 BenH, IBM Corporation.
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public
      8 * License as published by the Free Software Foundation; either
      9 * version 2.1 of the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful,
     12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef PPC_PNV_H
     21#define PPC_PNV_H
     22
     23#include "hw/boards.h"
     24#include "hw/sysbus.h"
     25#include "hw/ipmi/ipmi.h"
     26#include "hw/ppc/pnv_lpc.h"
     27#include "hw/ppc/pnv_pnor.h"
     28#include "hw/ppc/pnv_psi.h"
     29#include "hw/ppc/pnv_occ.h"
     30#include "hw/ppc/pnv_homer.h"
     31#include "hw/ppc/pnv_xive.h"
     32#include "hw/ppc/pnv_core.h"
     33#include "hw/pci-host/pnv_phb3.h"
     34#include "hw/pci-host/pnv_phb4.h"
     35#include "qom/object.h"
     36
     37#define TYPE_PNV_CHIP "pnv-chip"
     38OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
     39                    PNV_CHIP)
     40
     41struct PnvChip {
     42    /*< private >*/
     43    SysBusDevice parent_obj;
     44
     45    /*< public >*/
     46    uint32_t     chip_id;
     47    uint64_t     ram_start;
     48    uint64_t     ram_size;
     49
     50    uint32_t     nr_cores;
     51    uint32_t     nr_threads;
     52    uint64_t     cores_mask;
     53    PnvCore      **cores;
     54
     55    uint32_t     num_phbs;
     56
     57    MemoryRegion xscom_mmio;
     58    MemoryRegion xscom;
     59    AddressSpace xscom_as;
     60
     61    MemoryRegion *fw_mr;
     62    gchar        *dt_isa_nodename;
     63};
     64
     65#define TYPE_PNV8_CHIP "pnv8-chip"
     66typedef struct Pnv8Chip Pnv8Chip;
     67DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
     68                         TYPE_PNV8_CHIP)
     69
     70struct Pnv8Chip {
     71    /*< private >*/
     72    PnvChip      parent_obj;
     73
     74    /*< public >*/
     75    MemoryRegion icp_mmio;
     76
     77    PnvLpcController lpc;
     78    Pnv8Psi      psi;
     79    PnvOCC       occ;
     80    PnvHomer     homer;
     81
     82#define PNV8_CHIP_PHB3_MAX 4
     83    PnvPHB3      phbs[PNV8_CHIP_PHB3_MAX];
     84
     85    XICSFabric    *xics;
     86};
     87
     88#define TYPE_PNV9_CHIP "pnv9-chip"
     89typedef struct Pnv9Chip Pnv9Chip;
     90DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
     91                         TYPE_PNV9_CHIP)
     92
     93struct Pnv9Chip {
     94    /*< private >*/
     95    PnvChip      parent_obj;
     96
     97    /*< public >*/
     98    PnvXive      xive;
     99    Pnv9Psi      psi;
    100    PnvLpcController lpc;
    101    PnvOCC       occ;
    102    PnvHomer     homer;
    103
    104    uint32_t     nr_quads;
    105    PnvQuad      *quads;
    106
    107#define PNV9_CHIP_MAX_PEC 3
    108    PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
    109};
    110
    111/*
    112 * A SMT8 fused core is a pair of SMT4 cores.
    113 */
    114#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
    115#define PNV9_PIR2CHIP(pir)      (((pir) >> 8) & 0x7f)
    116
    117#define TYPE_PNV10_CHIP "pnv10-chip"
    118typedef struct Pnv10Chip Pnv10Chip;
    119DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
    120                         TYPE_PNV10_CHIP)
    121
    122struct Pnv10Chip {
    123    /*< private >*/
    124    PnvChip      parent_obj;
    125
    126    /*< public >*/
    127    Pnv9Psi      psi;
    128    PnvLpcController lpc;
    129};
    130
    131struct PnvChipClass {
    132    /*< private >*/
    133    SysBusDeviceClass parent_class;
    134
    135    /*< public >*/
    136    uint64_t     chip_cfam_id;
    137    uint64_t     cores_mask;
    138    uint32_t     num_phbs;
    139
    140    DeviceRealize parent_realize;
    141
    142    uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
    143    void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
    144    void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
    145    void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
    146    void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
    147    ISABus *(*isa_create)(PnvChip *chip, Error **errp);
    148    void (*dt_populate)(PnvChip *chip, void *fdt);
    149    void (*pic_print_info)(PnvChip *chip, Monitor *mon);
    150    uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
    151    uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
    152};
    153
    154#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
    155#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
    156
    157#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
    158DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
    159                         TYPE_PNV_CHIP_POWER8E)
    160
    161#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
    162DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
    163                         TYPE_PNV_CHIP_POWER8)
    164
    165#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
    166DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
    167                         TYPE_PNV_CHIP_POWER8NVL)
    168
    169#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
    170DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
    171                         TYPE_PNV_CHIP_POWER9)
    172
    173#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
    174DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
    175                         TYPE_PNV_CHIP_POWER10)
    176
    177PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
    178
    179#define TYPE_PNV_MACHINE       MACHINE_TYPE_NAME("powernv")
    180typedef struct PnvMachineClass PnvMachineClass;
    181typedef struct PnvMachineState PnvMachineState;
    182DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
    183                     PNV_MACHINE, TYPE_PNV_MACHINE)
    184
    185
    186struct PnvMachineClass {
    187    /*< private >*/
    188    MachineClass parent_class;
    189
    190    /*< public >*/
    191    const char *compat;
    192    int compat_size;
    193
    194    void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
    195};
    196
    197struct PnvMachineState {
    198    /*< private >*/
    199    MachineState parent_obj;
    200
    201    uint32_t     initrd_base;
    202    long         initrd_size;
    203
    204    uint32_t     num_chips;
    205    PnvChip      **chips;
    206
    207    ISABus       *isa_bus;
    208    uint32_t     cpld_irqstate;
    209
    210    IPMIBmc      *bmc;
    211    Notifier     powerdown_notifier;
    212
    213    PnvPnor      *pnor;
    214
    215    hwaddr       fw_load_addr;
    216};
    217
    218#define PNV_FDT_ADDR          0x01000000
    219#define PNV_TIMEBASE_FREQ     512000000ULL
    220
    221/*
    222 * BMC helpers
    223 */
    224void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
    225void pnv_bmc_powerdown(IPMIBmc *bmc);
    226IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
    227IPMIBmc *pnv_bmc_find(Error **errp);
    228void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
    229
    230/*
    231 * POWER8 MMIO base addresses
    232 */
    233#define PNV_XSCOM_SIZE        0x800000000ull
    234#define PNV_XSCOM_BASE(chip)                                            \
    235    (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
    236
    237#define PNV_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
    238#define PNV_OCC_COMMON_AREA_BASE    0x7fff800000ull
    239#define PNV_OCC_SENSOR_BASE(chip)   (PNV_OCC_COMMON_AREA_BASE + \
    240    PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
    241
    242#define PNV_HOMER_SIZE              0x0000000000400000ull
    243#define PNV_HOMER_BASE(chip)                                            \
    244    (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
    245
    246
    247/*
    248 * XSCOM 0x20109CA defines the ICP BAR:
    249 *
    250 * 0:29   : bits 14 to 43 of address to define 1 MB region.
    251 * 30     : 1 to enable ICP to receive loads/stores against its BAR region
    252 * 31:63  : Constant 0
    253 *
    254 * Usually defined as :
    255 *
    256 *      0xffffe00200000000 -> 0x0003ffff80000000
    257 *      0xffffe00600000000 -> 0x0003ffff80100000
    258 *      0xffffe02200000000 -> 0x0003ffff80800000
    259 *      0xffffe02600000000 -> 0x0003ffff80900000
    260 */
    261#define PNV_ICP_SIZE         0x0000000000100000ull
    262#define PNV_ICP_BASE(chip)                                              \
    263    (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
    264
    265
    266#define PNV_PSIHB_SIZE       0x0000000000100000ull
    267#define PNV_PSIHB_BASE(chip) \
    268    (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
    269
    270#define PNV_PSIHB_FSP_SIZE   0x0000000100000000ull
    271#define PNV_PSIHB_FSP_BASE(chip) \
    272    (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
    273     PNV_PSIHB_FSP_SIZE)
    274
    275/*
    276 * POWER9 MMIO base addresses
    277 */
    278#define PNV9_CHIP_BASE(chip, base)   \
    279    ((base) + ((uint64_t) (chip)->chip_id << 42))
    280
    281#define PNV9_XIVE_VC_SIZE            0x0000008000000000ull
    282#define PNV9_XIVE_VC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
    283
    284#define PNV9_XIVE_PC_SIZE            0x0000001000000000ull
    285#define PNV9_XIVE_PC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
    286
    287#define PNV9_LPCM_SIZE               0x0000000100000000ull
    288#define PNV9_LPCM_BASE(chip)         PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
    289
    290#define PNV9_PSIHB_SIZE              0x0000000000100000ull
    291#define PNV9_PSIHB_BASE(chip)        PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
    292
    293#define PNV9_XIVE_IC_SIZE            0x0000000000080000ull
    294#define PNV9_XIVE_IC_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
    295
    296#define PNV9_XIVE_TM_SIZE            0x0000000000040000ull
    297#define PNV9_XIVE_TM_BASE(chip)      PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
    298
    299#define PNV9_PSIHB_ESB_SIZE          0x0000000000010000ull
    300#define PNV9_PSIHB_ESB_BASE(chip)    PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
    301
    302#define PNV9_XSCOM_SIZE              0x0000000400000000ull
    303#define PNV9_XSCOM_BASE(chip)        PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
    304
    305#define PNV9_OCC_COMMON_AREA_SIZE    0x0000000000800000ull
    306#define PNV9_OCC_COMMON_AREA_BASE    0x203fff800000ull
    307#define PNV9_OCC_SENSOR_BASE(chip)   (PNV9_OCC_COMMON_AREA_BASE +       \
    308    PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
    309
    310#define PNV9_HOMER_SIZE              0x0000000000400000ull
    311#define PNV9_HOMER_BASE(chip)                                           \
    312    (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
    313
    314/*
    315 * POWER10 MMIO base addresses - 16TB stride per chip
    316 */
    317#define PNV10_CHIP_BASE(chip, base)   \
    318    ((base) + ((uint64_t) (chip)->chip_id << 44))
    319
    320#define PNV10_XSCOM_SIZE             0x0000000400000000ull
    321#define PNV10_XSCOM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
    322
    323#define PNV10_LPCM_SIZE             0x0000000100000000ull
    324#define PNV10_LPCM_BASE(chip)       PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
    325
    326#define PNV10_PSIHB_ESB_SIZE        0x0000000000100000ull
    327#define PNV10_PSIHB_ESB_BASE(chip)  PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
    328
    329#define PNV10_PSIHB_SIZE            0x0000000000100000ull
    330#define PNV10_PSIHB_BASE(chip)      PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
    331
    332#endif /* PPC_PNV_H */