cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

pnv_core.h (1831B)

      1/*
      2 * QEMU PowerPC PowerNV CPU Core model
      3 *
      4 * Copyright (c) 2016, IBM Corporation.
      5 *
      6 * This library is free software; you can redistribute it and/or
      7 * modify it under the terms of the GNU Lesser General Public License
      8 * as published by the Free Software Foundation; either version 2.1 of
      9 * the License, or (at your option) any later version.
     10 *
     11 * This library is distributed in the hope that it will be useful, but
     12 * WITHOUT ANY WARRANTY; without even the implied warranty of
     13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14 * Lesser General Public License for more details.
     15 *
     16 * You should have received a copy of the GNU Lesser General Public
     17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef PPC_PNV_CORE_H
     21#define PPC_PNV_CORE_H
     22
     23#include "hw/cpu/core.h"
     24#include "target/ppc/cpu.h"
     25#include "qom/object.h"
     26
     27#define TYPE_PNV_CORE "powernv-cpu-core"
     28OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
     29                    PNV_CORE)
     30
     31typedef struct PnvChip PnvChip;
     32
     33struct PnvCore {
     34    /*< private >*/
     35    CPUCore parent_obj;
     36
     37    /*< public >*/
     38    PowerPCCPU **threads;
     39    uint32_t pir;
     40    uint64_t hrmor;
     41    PnvChip *chip;
     42
     43    MemoryRegion xscom_regs;
     44};
     45
     46struct PnvCoreClass {
     47    DeviceClass parent_class;
     48
     49    const MemoryRegionOps *xscom_ops;
     50};
     51
     52#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
     53#define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
     54
     55typedef struct PnvCPUState {
     56    Object *intc;
     57} PnvCPUState;
     58
     59static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
     60{
     61    return (PnvCPUState *)cpu->machine_data;
     62}
     63
     64#define TYPE_PNV_QUAD "powernv-cpu-quad"
     65OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
     66
     67struct PnvQuad {
     68    DeviceState parent_obj;
     69
     70    uint32_t quad_id;
     71    MemoryRegion xscom_regs;
     72};
     73#endif /* PPC_PNV_CORE_H */