spapr.h (38835B)
1#ifndef HW_SPAPR_H 2#define HW_SPAPR_H 3 4#include "qemu/units.h" 5#include "sysemu/dma.h" 6#include "hw/boards.h" 7#include "hw/ppc/spapr_drc.h" 8#include "hw/mem/pc-dimm.h" 9#include "hw/ppc/spapr_ovec.h" 10#include "hw/ppc/spapr_irq.h" 11#include "qom/object.h" 12#include "hw/ppc/spapr_xive.h" /* For SpaprXive */ 13#include "hw/ppc/xics.h" /* For ICSState */ 14#include "hw/ppc/spapr_tpm_proxy.h" 15#include "hw/ppc/vof.h" 16 17struct SpaprVioBus; 18struct SpaprPhbState; 19struct SpaprNvram; 20 21typedef struct SpaprEventLogEntry SpaprEventLogEntry; 22typedef struct SpaprEventSource SpaprEventSource; 23typedef struct SpaprPendingHpt SpaprPendingHpt; 24 25#define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL 26#define SPAPR_ENTRY_POINT 0x100 27 28#define SPAPR_TIMEBASE_FREQ 512000000ULL 29 30#define TYPE_SPAPR_RTC "spapr-rtc" 31 32OBJECT_DECLARE_SIMPLE_TYPE(SpaprRtcState, SPAPR_RTC) 33 34struct SpaprRtcState { 35 /*< private >*/ 36 DeviceState parent_obj; 37 int64_t ns_offset; 38}; 39 40typedef struct SpaprDimmState SpaprDimmState; 41 42#define TYPE_SPAPR_MACHINE "spapr-machine" 43OBJECT_DECLARE_TYPE(SpaprMachineState, SpaprMachineClass, SPAPR_MACHINE) 44 45typedef enum { 46 SPAPR_RESIZE_HPT_DEFAULT = 0, 47 SPAPR_RESIZE_HPT_DISABLED, 48 SPAPR_RESIZE_HPT_ENABLED, 49 SPAPR_RESIZE_HPT_REQUIRED, 50} SpaprResizeHpt; 51 52/** 53 * Capabilities 54 */ 55 56/* Hardware Transactional Memory */ 57#define SPAPR_CAP_HTM 0x00 58/* Vector Scalar Extensions */ 59#define SPAPR_CAP_VSX 0x01 60/* Decimal Floating Point */ 61#define SPAPR_CAP_DFP 0x02 62/* Cache Flush on Privilege Change */ 63#define SPAPR_CAP_CFPC 0x03 64/* Speculation Barrier Bounds Checking */ 65#define SPAPR_CAP_SBBC 0x04 66/* Indirect Branch Serialisation */ 67#define SPAPR_CAP_IBS 0x05 68/* HPT Maximum Page Size (encoded as a shift) */ 69#define SPAPR_CAP_HPT_MAXPAGESIZE 0x06 70/* Nested KVM-HV */ 71#define SPAPR_CAP_NESTED_KVM_HV 0x07 72/* Large Decrementer */ 73#define SPAPR_CAP_LARGE_DECREMENTER 0x08 74/* Count Cache Flush Assist HW Instruction */ 75#define SPAPR_CAP_CCF_ASSIST 0x09 76/* Implements PAPR FWNMI option */ 77#define SPAPR_CAP_FWNMI 0x0A 78/* Support H_RPT_INVALIDATE */ 79#define SPAPR_CAP_RPT_INVALIDATE 0x0B 80/* Num Caps */ 81#define SPAPR_CAP_NUM (SPAPR_CAP_RPT_INVALIDATE + 1) 82 83/* 84 * Capability Values 85 */ 86/* Bool Caps */ 87#define SPAPR_CAP_OFF 0x00 88#define SPAPR_CAP_ON 0x01 89 90/* Custom Caps */ 91 92/* Generic */ 93#define SPAPR_CAP_BROKEN 0x00 94#define SPAPR_CAP_WORKAROUND 0x01 95#define SPAPR_CAP_FIXED 0x02 96/* SPAPR_CAP_IBS (cap-ibs) */ 97#define SPAPR_CAP_FIXED_IBS 0x02 98#define SPAPR_CAP_FIXED_CCD 0x03 99#define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */ 100 101#define FDT_MAX_SIZE 0x200000 102 103/* Max number of GPUs per system */ 104#define NVGPU_MAX_NUM 6 105 106/* Max number of NUMA nodes */ 107#define NUMA_NODES_MAX_NUM (MAX_NODES + NVGPU_MAX_NUM) 108 109/* 110 * NUMA FORM1 macros. FORM1_DIST_REF_POINTS was taken from 111 * MAX_DISTANCE_REF_POINTS in arch/powerpc/mm/numa.h from Linux 112 * kernel source. It represents the amount of associativity domains 113 * for non-CPU resources. 114 * 115 * FORM1_NUMA_ASSOC_SIZE is the base array size of an ibm,associativity 116 * array for any non-CPU resource. 117 */ 118#define FORM1_DIST_REF_POINTS 4 119#define FORM1_NUMA_ASSOC_SIZE (FORM1_DIST_REF_POINTS + 1) 120 121/* 122 * FORM2 NUMA affinity has a single associativity domain, giving 123 * us a assoc size of 2. 124 */ 125#define FORM2_DIST_REF_POINTS 1 126#define FORM2_NUMA_ASSOC_SIZE (FORM2_DIST_REF_POINTS + 1) 127 128typedef struct SpaprCapabilities SpaprCapabilities; 129struct SpaprCapabilities { 130 uint8_t caps[SPAPR_CAP_NUM]; 131}; 132 133/** 134 * SpaprMachineClass: 135 */ 136struct SpaprMachineClass { 137 /*< private >*/ 138 MachineClass parent_class; 139 140 /*< public >*/ 141 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */ 142 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 143 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */ 144 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */ 145 bool pre_2_10_has_unused_icps; 146 bool legacy_irq_allocation; 147 uint32_t nr_xirqs; 148 bool broken_host_serial_model; /* present real host info to the guest */ 149 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ 150 bool linux_pci_probe; 151 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */ 152 hwaddr rma_limit; /* clamp the RMA to this size */ 153 bool pre_5_1_assoc_refpoints; 154 bool pre_5_2_numa_associativity; 155 bool pre_6_2_numa_affinity; 156 157 bool (*phb_placement)(SpaprMachineState *spapr, uint32_t index, 158 uint64_t *buid, hwaddr *pio, 159 hwaddr *mmio32, hwaddr *mmio64, 160 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa, 161 hwaddr *nv2atsd, Error **errp); 162 SpaprResizeHpt resize_hpt_default; 163 SpaprCapabilities default_caps; 164 SpaprIrq *irq; 165}; 166 167/** 168 * SpaprMachineState: 169 */ 170struct SpaprMachineState { 171 /*< private >*/ 172 MachineState parent_obj; 173 174 struct SpaprVioBus *vio_bus; 175 QLIST_HEAD(, SpaprPhbState) phbs; 176 struct SpaprNvram *nvram; 177 SpaprRtcState rtc; 178 179 SpaprResizeHpt resize_hpt; 180 void *htab; 181 uint32_t htab_shift; 182 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ 183 SpaprPendingHpt *pending_hpt; /* in-progress resize */ 184 185 hwaddr rma_size; 186 uint32_t fdt_size; 187 uint32_t fdt_initial_size; 188 void *fdt_blob; 189 long kernel_size; 190 bool kernel_le; 191 uint64_t kernel_addr; 192 uint32_t initrd_base; 193 long initrd_size; 194 Vof *vof; 195 uint64_t rtc_offset; /* Now used only during incoming migration */ 196 struct PPCTimebase tb; 197 bool has_graphics; 198 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */ 199 200 Notifier epow_notifier; 201 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events; 202 bool use_hotplug_event_source; 203 SpaprEventSource *event_sources; 204 205 /* ibm,client-architecture-support option negotiation */ 206 bool cas_pre_isa3_guest; 207 SpaprOptionVector *ov5; /* QEMU-supported option vectors */ 208 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */ 209 uint32_t max_compat_pvr; 210 211 /* Migration state */ 212 int htab_save_index; 213 bool htab_first_pass; 214 int htab_fd; 215 216 /* Pending DIMM unplug cache. It is populated when a LMB 217 * unplug starts. It can be regenerated if a migration 218 * occurs during the unplug process. */ 219 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs; 220 221 /* State related to FWNMI option */ 222 223 /* System Reset and Machine Check Notification Routine addresses 224 * registered by "ibm,nmi-register" RTAS call. 225 */ 226 target_ulong fwnmi_system_reset_addr; 227 target_ulong fwnmi_machine_check_addr; 228 229 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is 230 * set to -1 if a FWNMI machine check is not in progress, else is set to 231 * the CPU that was delivered the machine check, and is set back to -1 232 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used 233 * to synchronize other CPUs. 234 */ 235 int fwnmi_machine_check_interlock; 236 QemuCond fwnmi_machine_check_interlock_cond; 237 238 /* Set by -boot */ 239 char *boot_device; 240 241 /*< public >*/ 242 char *kvm_type; 243 char *host_model; 244 char *host_serial; 245 246 int32_t irq_map_nr; 247 unsigned long *irq_map; 248 SpaprIrq *irq; 249 qemu_irq *qirqs; 250 SpaprInterruptController *active_intc; 251 ICSState *ics; 252 SpaprXive *xive; 253 254 bool cmd_line_caps[SPAPR_CAP_NUM]; 255 SpaprCapabilities def, eff, mig; 256 257 unsigned gpu_numa_id; 258 SpaprTpmProxy *tpm_proxy; 259 260 uint32_t FORM1_assoc_array[NUMA_NODES_MAX_NUM][FORM1_NUMA_ASSOC_SIZE]; 261 uint32_t FORM2_assoc_array[NUMA_NODES_MAX_NUM][FORM2_NUMA_ASSOC_SIZE]; 262 263 Error *fwnmi_migration_blocker; 264}; 265 266#define H_SUCCESS 0 267#define H_BUSY 1 /* Hardware busy -- retry later */ 268#define H_CLOSED 2 /* Resource closed */ 269#define H_NOT_AVAILABLE 3 270#define H_CONSTRAINED 4 /* Resource request constrained to max allowed */ 271#define H_PARTIAL 5 272#define H_IN_PROGRESS 14 /* Kind of like busy */ 273#define H_PAGE_REGISTERED 15 274#define H_PARTIAL_STORE 16 275#define H_PENDING 17 /* returned from H_POLL_PENDING */ 276#define H_CONTINUE 18 /* Returned from H_Join on success */ 277#define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */ 278#define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \ 279 is a good time to retry */ 280#define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \ 281 is a good time to retry */ 282#define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \ 283 is a good time to retry */ 284#define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \ 285 is a good time to retry */ 286#define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \ 287 is a good time to retry */ 288#define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \ 289 is a good time to retry */ 290#define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */ 291#define H_HARDWARE -1 /* Hardware error */ 292#define H_FUNCTION -2 /* Function not supported */ 293#define H_PRIVILEGE -3 /* Caller not privileged */ 294#define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */ 295#define H_BAD_MODE -5 /* Illegal msr value */ 296#define H_PTEG_FULL -6 /* PTEG is full */ 297#define H_NOT_FOUND -7 /* PTE was not found" */ 298#define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */ 299#define H_NO_MEM -9 300#define H_AUTHORITY -10 301#define H_PERMISSION -11 302#define H_DROPPED -12 303#define H_SOURCE_PARM -13 304#define H_DEST_PARM -14 305#define H_REMOTE_PARM -15 306#define H_RESOURCE -16 307#define H_ADAPTER_PARM -17 308#define H_RH_PARM -18 309#define H_RCQ_PARM -19 310#define H_SCQ_PARM -20 311#define H_EQ_PARM -21 312#define H_RT_PARM -22 313#define H_ST_PARM -23 314#define H_SIGT_PARM -24 315#define H_TOKEN_PARM -25 316#define H_MLENGTH_PARM -27 317#define H_MEM_PARM -28 318#define H_MEM_ACCESS_PARM -29 319#define H_ATTR_PARM -30 320#define H_PORT_PARM -31 321#define H_MCG_PARM -32 322#define H_VL_PARM -33 323#define H_TSIZE_PARM -34 324#define H_TRACE_PARM -35 325 326#define H_MASK_PARM -37 327#define H_MCG_FULL -38 328#define H_ALIAS_EXIST -39 329#define H_P_COUNTER -40 330#define H_TABLE_FULL -41 331#define H_ALT_TABLE -42 332#define H_MR_CONDITION -43 333#define H_NOT_ENOUGH_RESOURCES -44 334#define H_R_STATE -45 335#define H_RESCINDEND -46 336#define H_P2 -55 337#define H_P3 -56 338#define H_P4 -57 339#define H_P5 -58 340#define H_P6 -59 341#define H_P7 -60 342#define H_P8 -61 343#define H_P9 -62 344#define H_OVERLAP -68 345#define H_UNSUPPORTED_FLAG -256 346#define H_MULTI_THREADS_ACTIVE -9005 347 348 349/* Long Busy is a condition that can be returned by the firmware 350 * when a call cannot be completed now, but the identical call 351 * should be retried later. This prevents calls blocking in the 352 * firmware for long periods of time. Annoyingly the firmware can return 353 * a range of return codes, hinting at how long we should wait before 354 * retrying. If you don't care for the hint, the macro below is a good 355 * way to check for the long_busy return codes 356 */ 357#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \ 358 && (x <= H_LONG_BUSY_END_RANGE)) 359 360/* Flags */ 361#define H_LARGE_PAGE (1ULL<<(63-16)) 362#define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */ 363#define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */ 364#define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */ 365#define H_PAGE_STATE_CHANGE (1ULL<<(63-28)) 366#define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30))) 367#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED) 368#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31))) 369#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE 370#define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */ 371#define H_ANDCOND (1ULL<<(63-33)) 372#define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */ 373#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */ 374#define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */ 375#define H_COPY_PAGE (1ULL<<(63-49)) 376#define H_N (1ULL<<(63-61)) 377#define H_PP1 (1ULL<<(63-62)) 378#define H_PP2 (1ULL<<(63-63)) 379 380/* Values for 2nd argument to H_SET_MODE */ 381#define H_SET_MODE_RESOURCE_SET_CIABR 1 382#define H_SET_MODE_RESOURCE_SET_DAWR0 2 383#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3 384#define H_SET_MODE_RESOURCE_LE 4 385 386/* Flags for H_SET_MODE_RESOURCE_LE */ 387#define H_SET_MODE_ENDIAN_BIG 0 388#define H_SET_MODE_ENDIAN_LITTLE 1 389 390/* VASI States */ 391#define H_VASI_INVALID 0 392#define H_VASI_ENABLED 1 393#define H_VASI_ABORTED 2 394#define H_VASI_SUSPENDING 3 395#define H_VASI_SUSPENDED 4 396#define H_VASI_RESUMED 5 397#define H_VASI_COMPLETED 6 398 399/* DABRX flags */ 400#define H_DABRX_HYPERVISOR (1ULL<<(63-61)) 401#define H_DABRX_KERNEL (1ULL<<(63-62)) 402#define H_DABRX_USER (1ULL<<(63-63)) 403 404/* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */ 405#define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0) 406#define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1) 407#define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2) 408#define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3) 409#define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4) 410#define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5) 411#define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6) 412#define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7) 413#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9) 414 415#define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0) 416#define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1) 417#define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2) 418#define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5) 419#define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7) 420#define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8) 421 422/* Each control block has to be on a 4K boundary */ 423#define H_CB_ALIGNMENT 4096 424 425/* pSeries hypervisor opcodes */ 426#define H_REMOVE 0x04 427#define H_ENTER 0x08 428#define H_READ 0x0c 429#define H_CLEAR_MOD 0x10 430#define H_CLEAR_REF 0x14 431#define H_PROTECT 0x18 432#define H_GET_TCE 0x1c 433#define H_PUT_TCE 0x20 434#define H_SET_SPRG0 0x24 435#define H_SET_DABR 0x28 436#define H_PAGE_INIT 0x2c 437#define H_SET_ASR 0x30 438#define H_ASR_ON 0x34 439#define H_ASR_OFF 0x38 440#define H_LOGICAL_CI_LOAD 0x3c 441#define H_LOGICAL_CI_STORE 0x40 442#define H_LOGICAL_CACHE_LOAD 0x44 443#define H_LOGICAL_CACHE_STORE 0x48 444#define H_LOGICAL_ICBI 0x4c 445#define H_LOGICAL_DCBF 0x50 446#define H_GET_TERM_CHAR 0x54 447#define H_PUT_TERM_CHAR 0x58 448#define H_REAL_TO_LOGICAL 0x5c 449#define H_HYPERVISOR_DATA 0x60 450#define H_EOI 0x64 451#define H_CPPR 0x68 452#define H_IPI 0x6c 453#define H_IPOLL 0x70 454#define H_XIRR 0x74 455#define H_PERFMON 0x7c 456#define H_MIGRATE_DMA 0x78 457#define H_REGISTER_VPA 0xDC 458#define H_CEDE 0xE0 459#define H_CONFER 0xE4 460#define H_PROD 0xE8 461#define H_GET_PPP 0xEC 462#define H_SET_PPP 0xF0 463#define H_PURR 0xF4 464#define H_PIC 0xF8 465#define H_REG_CRQ 0xFC 466#define H_FREE_CRQ 0x100 467#define H_VIO_SIGNAL 0x104 468#define H_SEND_CRQ 0x108 469#define H_COPY_RDMA 0x110 470#define H_REGISTER_LOGICAL_LAN 0x114 471#define H_FREE_LOGICAL_LAN 0x118 472#define H_ADD_LOGICAL_LAN_BUFFER 0x11C 473#define H_SEND_LOGICAL_LAN 0x120 474#define H_BULK_REMOVE 0x124 475#define H_MULTICAST_CTRL 0x130 476#define H_SET_XDABR 0x134 477#define H_STUFF_TCE 0x138 478#define H_PUT_TCE_INDIRECT 0x13C 479#define H_CHANGE_LOGICAL_LAN_MAC 0x14C 480#define H_VTERM_PARTNER_INFO 0x150 481#define H_REGISTER_VTERM 0x154 482#define H_FREE_VTERM 0x158 483#define H_RESET_EVENTS 0x15C 484#define H_ALLOC_RESOURCE 0x160 485#define H_FREE_RESOURCE 0x164 486#define H_MODIFY_QP 0x168 487#define H_QUERY_QP 0x16C 488#define H_REREGISTER_PMR 0x170 489#define H_REGISTER_SMR 0x174 490#define H_QUERY_MR 0x178 491#define H_QUERY_MW 0x17C 492#define H_QUERY_HCA 0x180 493#define H_QUERY_PORT 0x184 494#define H_MODIFY_PORT 0x188 495#define H_DEFINE_AQP1 0x18C 496#define H_GET_TRACE_BUFFER 0x190 497#define H_DEFINE_AQP0 0x194 498#define H_RESIZE_MR 0x198 499#define H_ATTACH_MCQP 0x19C 500#define H_DETACH_MCQP 0x1A0 501#define H_CREATE_RPT 0x1A4 502#define H_REMOVE_RPT 0x1A8 503#define H_REGISTER_RPAGES 0x1AC 504#define H_DISABLE_AND_GETC 0x1B0 505#define H_ERROR_DATA 0x1B4 506#define H_GET_HCA_INFO 0x1B8 507#define H_GET_PERF_COUNT 0x1BC 508#define H_MANAGE_TRACE 0x1C0 509#define H_GET_CPU_CHARACTERISTICS 0x1C8 510#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4 511#define H_QUERY_INT_STATE 0x1E4 512#define H_POLL_PENDING 0x1D8 513#define H_ILLAN_ATTRIBUTES 0x244 514#define H_MODIFY_HEA_QP 0x250 515#define H_QUERY_HEA_QP 0x254 516#define H_QUERY_HEA 0x258 517#define H_QUERY_HEA_PORT 0x25C 518#define H_MODIFY_HEA_PORT 0x260 519#define H_REG_BCMC 0x264 520#define H_DEREG_BCMC 0x268 521#define H_REGISTER_HEA_RPAGES 0x26C 522#define H_DISABLE_AND_GET_HEA 0x270 523#define H_GET_HEA_INFO 0x274 524#define H_ALLOC_HEA_RESOURCE 0x278 525#define H_ADD_CONN 0x284 526#define H_DEL_CONN 0x288 527#define H_JOIN 0x298 528#define H_VASI_STATE 0x2A4 529#define H_ENABLE_CRQ 0x2B0 530#define H_GET_EM_PARMS 0x2B8 531#define H_SET_MPP 0x2D0 532#define H_GET_MPP 0x2D4 533#define H_HOME_NODE_ASSOCIATIVITY 0x2EC 534#define H_XIRR_X 0x2FC 535#define H_RANDOM 0x300 536#define H_SET_MODE 0x31C 537#define H_RESIZE_HPT_PREPARE 0x36C 538#define H_RESIZE_HPT_COMMIT 0x370 539#define H_CLEAN_SLB 0x374 540#define H_INVALIDATE_PID 0x378 541#define H_REGISTER_PROC_TBL 0x37C 542#define H_SIGNAL_SYS_RESET 0x380 543 544#define H_INT_GET_SOURCE_INFO 0x3A8 545#define H_INT_SET_SOURCE_CONFIG 0x3AC 546#define H_INT_GET_SOURCE_CONFIG 0x3B0 547#define H_INT_GET_QUEUE_INFO 0x3B4 548#define H_INT_SET_QUEUE_CONFIG 0x3B8 549#define H_INT_GET_QUEUE_CONFIG 0x3BC 550#define H_INT_SET_OS_REPORTING_LINE 0x3C0 551#define H_INT_GET_OS_REPORTING_LINE 0x3C4 552#define H_INT_ESB 0x3C8 553#define H_INT_SYNC 0x3CC 554#define H_INT_RESET 0x3D0 555#define H_SCM_READ_METADATA 0x3E4 556#define H_SCM_WRITE_METADATA 0x3E8 557#define H_SCM_BIND_MEM 0x3EC 558#define H_SCM_UNBIND_MEM 0x3F0 559#define H_SCM_UNBIND_ALL 0x3FC 560#define H_SCM_HEALTH 0x400 561#define H_RPT_INVALIDATE 0x448 562 563#define MAX_HCALL_OPCODE H_RPT_INVALIDATE 564 565/* The hcalls above are standardized in PAPR and implemented by pHyp 566 * as well. 567 * 568 * We also need some hcalls which are specific to qemu / KVM-on-POWER. 569 * We put those into the 0xf000-0xfffc range which is reserved by PAPR 570 * for "platform-specific" hcalls. 571 */ 572#define KVMPPC_HCALL_BASE 0xf000 573#define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0) 574#define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1) 575/* Client Architecture support */ 576#define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2) 577#define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3) 578/* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */ 579#define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5) 580#define KVMPPC_HCALL_MAX KVMPPC_H_VOF_CLIENT 581 582/* 583 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating 584 * Secure VM mode via an Ultravisor / Protected Execution Facility 585 */ 586#define SVM_HCALL_BASE 0xEF00 587#define SVM_H_TPM_COMM 0xEF10 588#define SVM_HCALL_MAX SVM_H_TPM_COMM 589 590 591typedef struct SpaprDeviceTreeUpdateHeader { 592 uint32_t version_id; 593} SpaprDeviceTreeUpdateHeader; 594 595#define hcall_dprintf(fmt, ...) \ 596 do { \ 597 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \ 598 } while (0) 599 600typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 601 target_ulong opcode, 602 target_ulong *args); 603 604void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); 605target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 606 target_ulong *args); 607target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr, 608 target_ulong shift); 609target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr, 610 target_ulong flags, target_ulong shift); 611bool is_ram_address(SpaprMachineState *spapr, hwaddr addr); 612void push_sregs_to_kvm_pr(SpaprMachineState *spapr); 613 614/* Virtual Processor Area structure constants */ 615#define VPA_MIN_SIZE 640 616#define VPA_SIZE_OFFSET 0x4 617#define VPA_SHARED_PROC_OFFSET 0x9 618#define VPA_SHARED_PROC_VAL 0x2 619#define VPA_DISPATCH_COUNTER 0x100 620 621/* ibm,set-eeh-option */ 622#define RTAS_EEH_DISABLE 0 623#define RTAS_EEH_ENABLE 1 624#define RTAS_EEH_THAW_IO 2 625#define RTAS_EEH_THAW_DMA 3 626 627/* ibm,get-config-addr-info2 */ 628#define RTAS_GET_PE_ADDR 0 629#define RTAS_GET_PE_MODE 1 630#define RTAS_PE_MODE_NONE 0 631#define RTAS_PE_MODE_NOT_SHARED 1 632#define RTAS_PE_MODE_SHARED 2 633 634/* ibm,read-slot-reset-state2 */ 635#define RTAS_EEH_PE_STATE_NORMAL 0 636#define RTAS_EEH_PE_STATE_RESET 1 637#define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2 638#define RTAS_EEH_PE_STATE_STOPPED_DMA 4 639#define RTAS_EEH_PE_STATE_UNAVAIL 5 640#define RTAS_EEH_NOT_SUPPORT 0 641#define RTAS_EEH_SUPPORT 1 642#define RTAS_EEH_PE_UNAVAIL_INFO 1000 643#define RTAS_EEH_PE_RECOVER_INFO 0 644 645/* ibm,set-slot-reset */ 646#define RTAS_SLOT_RESET_DEACTIVATE 0 647#define RTAS_SLOT_RESET_HOT 1 648#define RTAS_SLOT_RESET_FUNDAMENTAL 3 649 650/* ibm,slot-error-detail */ 651#define RTAS_SLOT_TEMP_ERR_LOG 1 652#define RTAS_SLOT_PERM_ERR_LOG 2 653 654/* RTAS return codes */ 655#define RTAS_OUT_SUCCESS 0 656#define RTAS_OUT_NO_ERRORS_FOUND 1 657#define RTAS_OUT_HW_ERROR -1 658#define RTAS_OUT_BUSY -2 659#define RTAS_OUT_PARAM_ERROR -3 660#define RTAS_OUT_NOT_SUPPORTED -3 661#define RTAS_OUT_NO_SUCH_INDICATOR -3 662#define RTAS_OUT_NOT_AUTHORIZED -9002 663#define RTAS_OUT_SYSPARM_PARAM_ERROR -9999 664 665/* DDW pagesize mask values from ibm,query-pe-dma-window */ 666#define RTAS_DDW_PGSIZE_4K 0x01 667#define RTAS_DDW_PGSIZE_64K 0x02 668#define RTAS_DDW_PGSIZE_16M 0x04 669#define RTAS_DDW_PGSIZE_32M 0x08 670#define RTAS_DDW_PGSIZE_64M 0x10 671#define RTAS_DDW_PGSIZE_128M 0x20 672#define RTAS_DDW_PGSIZE_256M 0x40 673#define RTAS_DDW_PGSIZE_16G 0x80 674 675/* RTAS tokens */ 676#define RTAS_TOKEN_BASE 0x2000 677 678#define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00) 679#define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01) 680#define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02) 681#define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03) 682#define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04) 683#define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05) 684#define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06) 685#define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07) 686#define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08) 687#define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09) 688#define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A) 689#define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B) 690#define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C) 691#define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D) 692#define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E) 693#define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F) 694#define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10) 695#define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11) 696#define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12) 697#define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13) 698#define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14) 699#define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15) 700#define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16) 701#define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17) 702#define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18) 703#define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19) 704#define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A) 705#define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B) 706#define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C) 707#define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) 708#define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) 709#define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) 710#define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20) 711#define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21) 712#define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22) 713#define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23) 714#define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24) 715#define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25) 716#define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26) 717#define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27) 718#define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28) 719#define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29) 720#define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A) 721#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B) 722#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C) 723 724#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D) 725 726/* RTAS ibm,get-system-parameter token values */ 727#define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 728#define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42 729#define RTAS_SYSPARM_UUID 48 730 731/* RTAS indicator/sensor types 732 * 733 * as defined by PAPR+ 2.7 7.3.5.4, Table 41 734 * 735 * NOTE: currently only DR-related sensors are implemented here 736 */ 737#define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001 738#define RTAS_SENSOR_TYPE_DR 9002 739#define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003 740#define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE 741 742/* Possible values for the platform-processor-diagnostics-run-mode parameter 743 * of the RTAS ibm,get-system-parameter call. 744 */ 745#define DIAGNOSTICS_RUN_MODE_DISABLED 0 746#define DIAGNOSTICS_RUN_MODE_STAGGERED 1 747#define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2 748#define DIAGNOSTICS_RUN_MODE_PERIODIC 3 749 750static inline uint64_t ppc64_phys_to_real(uint64_t addr) 751{ 752 return addr & ~0xF000000000000000ULL; 753} 754 755static inline uint32_t rtas_ld(target_ulong phys, int n) 756{ 757 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n)); 758} 759 760static inline uint64_t rtas_ldq(target_ulong phys, int n) 761{ 762 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1); 763} 764 765static inline void rtas_st(target_ulong phys, int n, uint32_t val) 766{ 767 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val); 768} 769 770typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm, 771 uint32_t token, 772 uint32_t nargs, target_ulong args, 773 uint32_t nret, target_ulong rets); 774void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn); 775target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm, 776 uint32_t token, uint32_t nargs, target_ulong args, 777 uint32_t nret, target_ulong rets); 778void spapr_dt_rtas_tokens(void *fdt, int rtas); 779void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr); 780 781#define SPAPR_TCE_PAGE_SHIFT 12 782#define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT) 783#define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1) 784 785#define SPAPR_VIO_BASE_LIOBN 0x00000000 786#define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg)) 787#define SPAPR_PCI_LIOBN(phb_index, window_num) \ 788 (0x80000000 | ((phb_index) << 8) | (window_num)) 789#define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000)) 790#define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff) 791 792#define RTAS_MIN_SIZE 20 /* hv_rtas_size in SLOF */ 793#define RTAS_ERROR_LOG_MAX 2048 794 795/* Offset from rtas-base where error log is placed */ 796#define RTAS_ERROR_LOG_OFFSET 0x30 797 798#define RTAS_EVENT_SCAN_RATE 1 799 800/* This helper should be used to encode interrupt specifiers when the related 801 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie, 802 * VIO devices, RTAS event sources and PHBs). 803 */ 804static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi) 805{ 806 intspec[0] = cpu_to_be32(irq); 807 intspec[1] = is_lsi ? cpu_to_be32(1) : 0; 808} 809 810 811#define TYPE_SPAPR_TCE_TABLE "spapr-tce-table" 812OBJECT_DECLARE_SIMPLE_TYPE(SpaprTceTable, SPAPR_TCE_TABLE) 813 814#define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region" 815DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, SPAPR_IOMMU_MEMORY_REGION, 816 TYPE_SPAPR_IOMMU_MEMORY_REGION) 817 818struct SpaprTceTable { 819 DeviceState parent; 820 uint32_t liobn; 821 uint32_t nb_table; 822 uint64_t bus_offset; 823 uint32_t page_shift; 824 uint64_t *table; 825 uint32_t mig_nb_table; 826 uint64_t *mig_table; 827 bool bypass; 828 bool need_vfio; 829 bool skipping_replay; 830 int fd; 831 MemoryRegion root; 832 IOMMUMemoryRegion iommu; 833 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */ 834 QLIST_ENTRY(SpaprTceTable) list; 835}; 836 837SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn); 838 839struct SpaprEventLogEntry { 840 uint32_t summary; 841 uint32_t extended_length; 842 void *extended_log; 843 QTAILQ_ENTRY(SpaprEventLogEntry) next; 844}; 845 846void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space); 847void spapr_events_init(SpaprMachineState *sm); 848void spapr_dt_events(SpaprMachineState *sm, void *fdt); 849void close_htab_fd(SpaprMachineState *spapr); 850void spapr_setup_hpt(SpaprMachineState *spapr); 851void spapr_free_hpt(SpaprMachineState *spapr); 852void spapr_check_mmu_mode(bool guest_radix); 853SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn); 854void spapr_tce_table_enable(SpaprTceTable *tcet, 855 uint32_t page_shift, uint64_t bus_offset, 856 uint32_t nb_table); 857void spapr_tce_table_disable(SpaprTceTable *tcet); 858void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio); 859 860MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet); 861int spapr_dma_dt(void *fdt, int node_off, const char *propname, 862 uint32_t liobn, uint64_t window, uint32_t size); 863int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, 864 SpaprTceTable *tcet); 865void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian); 866void spapr_hotplug_req_add_by_index(SpaprDrc *drc); 867void spapr_hotplug_req_remove_by_index(SpaprDrc *drc); 868void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type, 869 uint32_t count); 870void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type, 871 uint32_t count); 872void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type, 873 uint32_t count, uint32_t index); 874void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type, 875 uint32_t count, uint32_t index); 876int spapr_hpt_shift_for_ramsize(uint64_t ramsize); 877int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp); 878void spapr_clear_pending_events(SpaprMachineState *spapr); 879void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr); 880void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev); 881int spapr_max_server_number(SpaprMachineState *spapr); 882void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 883 uint64_t pte0, uint64_t pte1); 884void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered); 885 886/* DRC callbacks. */ 887void spapr_core_release(DeviceState *dev); 888int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 889 void *fdt, int *fdt_start_offset, Error **errp); 890void spapr_lmb_release(DeviceState *dev); 891int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 892 void *fdt, int *fdt_start_offset, Error **errp); 893void spapr_phb_release(DeviceState *dev); 894int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 895 void *fdt, int *fdt_start_offset, Error **errp); 896 897void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns); 898int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset); 899 900#define TYPE_SPAPR_RNG "spapr-rng" 901 902#define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */ 903 904/* 905 * This defines the maximum number of DIMM slots we can have for sPAPR 906 * guest. This is not defined by sPAPR but we are defining it to 32 slots 907 * based on default number of slots provided by PowerPC kernel. 908 */ 909#define SPAPR_MAX_RAM_SLOTS 32 910 911/* 1GB alignment for hotplug memory region */ 912#define SPAPR_DEVICE_MEM_ALIGN (1 * GiB) 913 914/* 915 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory 916 * property under ibm,dynamic-reconfiguration-memory node. 917 */ 918#define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6 919 920/* 921 * Defines for flag value in ibm,dynamic-memory property under 922 * ibm,dynamic-reconfiguration-memory node. 923 */ 924#define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008 925#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020 926#define SPAPR_LMB_FLAGS_RESERVED 0x00000080 927#define SPAPR_LMB_FLAGS_HOTREMOVABLE 0x00000100 928 929void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg); 930 931#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 932 933int spapr_get_vcpu_id(PowerPCCPU *cpu); 934bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp); 935PowerPCCPU *spapr_find_cpu(int vcpu_id); 936 937int spapr_caps_pre_load(void *opaque); 938int spapr_caps_pre_save(void *opaque); 939 940/* 941 * Handling of optional capabilities 942 */ 943extern const VMStateDescription vmstate_spapr_cap_htm; 944extern const VMStateDescription vmstate_spapr_cap_vsx; 945extern const VMStateDescription vmstate_spapr_cap_dfp; 946extern const VMStateDescription vmstate_spapr_cap_cfpc; 947extern const VMStateDescription vmstate_spapr_cap_sbbc; 948extern const VMStateDescription vmstate_spapr_cap_ibs; 949extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize; 950extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv; 951extern const VMStateDescription vmstate_spapr_cap_large_decr; 952extern const VMStateDescription vmstate_spapr_cap_ccf_assist; 953extern const VMStateDescription vmstate_spapr_cap_fwnmi; 954extern const VMStateDescription vmstate_spapr_cap_rpt_invalidate; 955 956static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap) 957{ 958 return spapr->eff.caps[cap]; 959} 960 961void spapr_caps_init(SpaprMachineState *spapr); 962void spapr_caps_apply(SpaprMachineState *spapr); 963void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu); 964void spapr_caps_add_properties(SpaprMachineClass *smc); 965int spapr_caps_post_migration(SpaprMachineState *spapr); 966 967bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, 968 Error **errp); 969/* 970 * XIVE definitions 971 */ 972#define SPAPR_OV5_XIVE_LEGACY 0x0 973#define SPAPR_OV5_XIVE_EXPLOIT 0x40 974#define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ 975 976void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); 977hwaddr spapr_get_rtas_addr(void); 978bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); 979 980void spapr_vof_reset(SpaprMachineState *spapr, void *fdt, Error **errp); 981void spapr_vof_quiesce(MachineState *ms); 982bool spapr_vof_setprop(MachineState *ms, const char *path, const char *propname, 983 void *val, int vallen); 984target_ulong spapr_h_vof_client(PowerPCCPU *cpu, SpaprMachineState *spapr, 985 target_ulong opcode, target_ulong *args); 986target_ulong spapr_vof_client_architecture_support(MachineState *ms, 987 CPUState *cs, 988 target_ulong ovec_addr); 989void spapr_vof_client_dt_finalize(SpaprMachineState *spapr, void *fdt); 990 991#endif /* HW_SPAPR_H */