cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

boot.h (2818B)

      1/*
      2 * QEMU RISC-V Boot Helper
      3 *
      4 * Copyright (c) 2017 SiFive, Inc.
      5 * Copyright (c) 2019 Alistair Francis <alistair.francis@wdc.com>
      6 *
      7 * This program is free software; you can redistribute it and/or modify it
      8 * under the terms and conditions of the GNU General Public License,
      9 * version 2 or later, as published by the Free Software Foundation.
     10 *
     11 * This program is distributed in the hope it will be useful, but WITHOUT
     12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     14 * more details.
     15 *
     16 * You should have received a copy of the GNU General Public License along with
     17 * this program.  If not, see <http://www.gnu.org/licenses/>.
     18 */
     19
     20#ifndef RISCV_BOOT_H
     21#define RISCV_BOOT_H
     22
     23#include "exec/cpu-defs.h"
     24#include "hw/loader.h"
     25#include "hw/riscv/riscv_hart.h"
     26
     27#define RISCV32_BIOS_BIN    "opensbi-riscv32-generic-fw_dynamic.bin"
     28#define RISCV32_BIOS_ELF    "opensbi-riscv32-generic-fw_dynamic.elf"
     29#define RISCV64_BIOS_BIN    "opensbi-riscv64-generic-fw_dynamic.bin"
     30#define RISCV64_BIOS_ELF    "opensbi-riscv64-generic-fw_dynamic.elf"
     31
     32bool riscv_is_32bit(RISCVHartArrayState *harts);
     33
     34target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
     35                                          target_ulong firmware_end_addr);
     36target_ulong riscv_find_and_load_firmware(MachineState *machine,
     37                                          const char *default_machine_firmware,
     38                                          hwaddr firmware_load_addr,
     39                                          symbol_fn_t sym_cb);
     40char *riscv_find_firmware(const char *firmware_filename);
     41target_ulong riscv_load_firmware(const char *firmware_filename,
     42                                 hwaddr firmware_load_addr,
     43                                 symbol_fn_t sym_cb);
     44target_ulong riscv_load_kernel(const char *kernel_filename,
     45                               target_ulong firmware_end_addr,
     46                               symbol_fn_t sym_cb);
     47hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
     48                         uint64_t kernel_entry, hwaddr *start);
     49uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
     50void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
     51                               hwaddr saddr,
     52                               hwaddr rom_base, hwaddr rom_size,
     53                               uint64_t kernel_entry,
     54                               uint32_t fdt_load_addr, void *fdt);
     55void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
     56                                  hwaddr rom_size,
     57                                  uint32_t reset_vec_size,
     58                                  uint64_t kernel_entry);
     59
     60#endif /* RISCV_BOOT_H */