cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
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shakti_c.h (2132B)

      1/*
      2 * Shakti C-class SoC emulation
      3 *
      4 * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
      5 *
      6 * This program is free software; you can redistribute it and/or modify it
      7 * under the terms and conditions of the GNU General Public License,
      8 * version 2 or later, as published by the Free Software Foundation.
      9 *
     10 * This program is distributed in the hope it will be useful, but WITHOUT
     11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     13 * more details.
     14 *
     15 * You should have received a copy of the GNU General Public License along with
     16 * this program.  If not, see <http://www.gnu.org/licenses/>.
     17 */
     18
     19#ifndef HW_SHAKTI_H
     20#define HW_SHAKTI_H
     21
     22#include "hw/riscv/riscv_hart.h"
     23#include "hw/boards.h"
     24#include "hw/char/shakti_uart.h"
     25
     26#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
     27#define RISCV_SHAKTI_SOC(obj) \
     28    OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
     29
     30typedef struct ShaktiCSoCState {
     31    /*< private >*/
     32    DeviceState parent_obj;
     33
     34    /*< public >*/
     35    RISCVHartArrayState cpus;
     36    DeviceState *plic;
     37    ShaktiUartState uart;
     38    MemoryRegion rom;
     39
     40} ShaktiCSoCState;
     41
     42#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
     43#define RISCV_SHAKTI_MACHINE(obj) \
     44    OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
     45typedef struct ShaktiCMachineState {
     46    /*< private >*/
     47    MachineState parent_obj;
     48
     49    /*< public >*/
     50    ShaktiCSoCState soc;
     51} ShaktiCMachineState;
     52
     53enum {
     54    SHAKTI_C_ROM,
     55    SHAKTI_C_RAM,
     56    SHAKTI_C_UART,
     57    SHAKTI_C_GPIO,
     58    SHAKTI_C_PLIC,
     59    SHAKTI_C_CLINT,
     60    SHAKTI_C_I2C,
     61};
     62
     63#define SHAKTI_C_PLIC_HART_CONFIG "MS"
     64/* Including Interrupt ID 0 (no interrupt)*/
     65#define SHAKTI_C_PLIC_NUM_SOURCES 28
     66/* Excluding Priority 0 */
     67#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
     68#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
     69#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
     70#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
     71#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
     72#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
     73#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
     74
     75#endif