cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

sifive_e.h (2455B)

      1/*
      2 * SiFive E series machine interface
      3 *
      4 * Copyright (c) 2017 SiFive, Inc.
      5 *
      6 * This program is free software; you can redistribute it and/or modify it
      7 * under the terms and conditions of the GNU General Public License,
      8 * version 2 or later, as published by the Free Software Foundation.
      9 *
     10 * This program is distributed in the hope it will be useful, but WITHOUT
     11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     12 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
     13 * more details.
     14 *
     15 * You should have received a copy of the GNU General Public License along with
     16 * this program.  If not, see <http://www.gnu.org/licenses/>.
     17 */
     18
     19#ifndef HW_SIFIVE_E_H
     20#define HW_SIFIVE_E_H
     21
     22#include "hw/riscv/riscv_hart.h"
     23#include "hw/riscv/sifive_cpu.h"
     24#include "hw/gpio/sifive_gpio.h"
     25
     26#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
     27#define RISCV_E_SOC(obj) \
     28    OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC)
     29
     30typedef struct SiFiveESoCState {
     31    /*< private >*/
     32    DeviceState parent_obj;
     33
     34    /*< public >*/
     35    RISCVHartArrayState cpus;
     36    DeviceState *plic;
     37    SIFIVEGPIOState gpio;
     38    MemoryRegion xip_mem;
     39    MemoryRegion mask_rom;
     40} SiFiveESoCState;
     41
     42typedef struct SiFiveEState {
     43    /*< private >*/
     44    SysBusDevice parent_obj;
     45
     46    /*< public >*/
     47    SiFiveESoCState soc;
     48    bool revb;
     49} SiFiveEState;
     50
     51#define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e")
     52#define RISCV_E_MACHINE(obj) \
     53    OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
     54
     55enum {
     56    SIFIVE_E_DEV_DEBUG,
     57    SIFIVE_E_DEV_MROM,
     58    SIFIVE_E_DEV_OTP,
     59    SIFIVE_E_DEV_CLINT,
     60    SIFIVE_E_DEV_PLIC,
     61    SIFIVE_E_DEV_AON,
     62    SIFIVE_E_DEV_PRCI,
     63    SIFIVE_E_DEV_OTP_CTRL,
     64    SIFIVE_E_DEV_GPIO0,
     65    SIFIVE_E_DEV_UART0,
     66    SIFIVE_E_DEV_QSPI0,
     67    SIFIVE_E_DEV_PWM0,
     68    SIFIVE_E_DEV_UART1,
     69    SIFIVE_E_DEV_QSPI1,
     70    SIFIVE_E_DEV_PWM1,
     71    SIFIVE_E_DEV_QSPI2,
     72    SIFIVE_E_DEV_PWM2,
     73    SIFIVE_E_DEV_XIP,
     74    SIFIVE_E_DEV_DTIM
     75};
     76
     77enum {
     78    SIFIVE_E_UART0_IRQ  = 3,
     79    SIFIVE_E_UART1_IRQ  = 4,
     80    SIFIVE_E_GPIO0_IRQ0 = 8
     81};
     82
     83#define SIFIVE_E_PLIC_HART_CONFIG "M"
     84#define SIFIVE_E_PLIC_NUM_SOURCES 127
     85#define SIFIVE_E_PLIC_NUM_PRIORITIES 7
     86#define SIFIVE_E_PLIC_PRIORITY_BASE 0x04
     87#define SIFIVE_E_PLIC_PENDING_BASE 0x1000
     88#define SIFIVE_E_PLIC_ENABLE_BASE 0x2000
     89#define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80
     90#define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000
     91#define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000
     92
     93#endif