cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

xlnx-zynqmp-rtc.h (3084B)

      1/*
      2 * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
      3 *
      4 * Copyright (c) 2017 Xilinx Inc.
      5 *
      6 * Written-by: Alistair Francis
      7 *
      8 * Permission is hereby granted, free of charge, to any person obtaining a copy
      9 * of this software and associated documentation files (the "Software"), to deal
     10 * in the Software without restriction, including without limitation the rights
     11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     12 * copies of the Software, and to permit persons to whom the Software is
     13 * furnished to do so, subject to the following conditions:
     14 *
     15 * The above copyright notice and this permission notice shall be included in
     16 * all copies or substantial portions of the Software.
     17 *
     18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     24 * THE SOFTWARE.
     25 */
     26
     27#ifndef HW_RTC_XLNX_ZYNQMP_H
     28#define HW_RTC_XLNX_ZYNQMP_H
     29
     30#include "hw/register.h"
     31#include "hw/sysbus.h"
     32#include "qom/object.h"
     33
     34#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc"
     35
     36OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPRTC, XLNX_ZYNQMP_RTC)
     37
     38REG32(SET_TIME_WRITE, 0x0)
     39REG32(SET_TIME_READ, 0x4)
     40REG32(CALIB_WRITE, 0x8)
     41    FIELD(CALIB_WRITE, FRACTION_EN, 20, 1)
     42    FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4)
     43    FIELD(CALIB_WRITE, MAX_TICK, 0, 16)
     44REG32(CALIB_READ, 0xc)
     45    FIELD(CALIB_READ, FRACTION_EN, 20, 1)
     46    FIELD(CALIB_READ, FRACTION_DATA, 16, 4)
     47    FIELD(CALIB_READ, MAX_TICK, 0, 16)
     48REG32(CURRENT_TIME, 0x10)
     49REG32(CURRENT_TICK, 0x14)
     50    FIELD(CURRENT_TICK, VALUE, 0, 16)
     51REG32(ALARM, 0x18)
     52REG32(RTC_INT_STATUS, 0x20)
     53    FIELD(RTC_INT_STATUS, ALARM, 1, 1)
     54    FIELD(RTC_INT_STATUS, SECONDS, 0, 1)
     55REG32(RTC_INT_MASK, 0x24)
     56    FIELD(RTC_INT_MASK, ALARM, 1, 1)
     57    FIELD(RTC_INT_MASK, SECONDS, 0, 1)
     58REG32(RTC_INT_EN, 0x28)
     59    FIELD(RTC_INT_EN, ALARM, 1, 1)
     60    FIELD(RTC_INT_EN, SECONDS, 0, 1)
     61REG32(RTC_INT_DIS, 0x2c)
     62    FIELD(RTC_INT_DIS, ALARM, 1, 1)
     63    FIELD(RTC_INT_DIS, SECONDS, 0, 1)
     64REG32(ADDR_ERROR, 0x30)
     65    FIELD(ADDR_ERROR, STATUS, 0, 1)
     66REG32(ADDR_ERROR_INT_MASK, 0x34)
     67    FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1)
     68REG32(ADDR_ERROR_INT_EN, 0x38)
     69    FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1)
     70REG32(ADDR_ERROR_INT_DIS, 0x3c)
     71    FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1)
     72REG32(CONTROL, 0x40)
     73    FIELD(CONTROL, BATTERY_DISABLE, 31, 1)
     74    FIELD(CONTROL, OSC_CNTRL, 24, 4)
     75    FIELD(CONTROL, SLVERR_ENABLE, 0, 1)
     76REG32(SAFETY_CHK, 0x50)
     77
     78#define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1)
     79
     80struct XlnxZynqMPRTC {
     81    SysBusDevice parent_obj;
     82    MemoryRegion iomem;
     83    qemu_irq irq_rtc_int;
     84    qemu_irq irq_addr_error_int;
     85
     86    uint32_t tick_offset;
     87
     88    uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX];
     89    RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX];
     90};
     91
     92#endif