cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

s390-pci-bus.h (11725B)

      1/*
      2 * s390 PCI BUS definitions
      3 *
      4 * Copyright 2014 IBM Corp.
      5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
      6 *            Hong Bo Li <lihbbj@cn.ibm.com>
      7 *            Yi Min Zhao <zyimin@cn.ibm.com>
      8 *
      9 * This work is licensed under the terms of the GNU GPL, version 2 or (at
     10 * your option) any later version. See the COPYING file in the top-level
     11 * directory.
     12 */
     13
     14#ifndef HW_S390_PCI_BUS_H
     15#define HW_S390_PCI_BUS_H
     16
     17#include "hw/pci/pci.h"
     18#include "hw/pci/pci_host.h"
     19#include "hw/s390x/sclp.h"
     20#include "hw/s390x/s390_flic.h"
     21#include "hw/s390x/css.h"
     22#include "hw/s390x/s390-pci-clp.h"
     23#include "qom/object.h"
     24
     25#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
     26#define TYPE_S390_PCI_BUS "s390-pcibus"
     27#define TYPE_S390_PCI_DEVICE "zpci"
     28#define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
     29#define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
     30#define FH_MASK_ENABLE   0x80000000
     31#define FH_MASK_INSTANCE 0x7f000000
     32#define FH_MASK_SHM      0x00ff0000
     33#define FH_MASK_INDEX    0x0000ffff
     34#define FH_SHM_VFIO      0x00010000
     35#define FH_SHM_EMUL      0x00020000
     36#define ZPCI_MAX_FID 0xffffffff
     37#define ZPCI_MAX_UID 0xffff
     38#define UID_UNDEFINED 0
     39#define UID_CHECKING_ENABLED 0x01
     40
     41OBJECT_DECLARE_SIMPLE_TYPE(S390pciState, S390_PCI_HOST_BRIDGE)
     42OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBus, S390_PCI_BUS)
     43OBJECT_DECLARE_SIMPLE_TYPE(S390PCIBusDevice, S390_PCI_DEVICE)
     44OBJECT_DECLARE_SIMPLE_TYPE(S390PCIIOMMU, S390_PCI_IOMMU)
     45
     46#define HP_EVENT_TO_CONFIGURED        0x0301
     47#define HP_EVENT_RESERVED_TO_STANDBY  0x0302
     48#define HP_EVENT_DECONFIGURE_REQUEST  0x0303
     49#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
     50#define HP_EVENT_STANDBY_TO_RESERVED  0x0308
     51
     52#define ERR_EVENT_INVALAS 0x1
     53#define ERR_EVENT_OORANGE 0x2
     54#define ERR_EVENT_INVALTF 0x3
     55#define ERR_EVENT_TPROTE  0x4
     56#define ERR_EVENT_APROTE  0x5
     57#define ERR_EVENT_KEYE    0x6
     58#define ERR_EVENT_INVALTE 0x7
     59#define ERR_EVENT_INVALTL 0x8
     60#define ERR_EVENT_TT      0x9
     61#define ERR_EVENT_INVALMS 0xa
     62#define ERR_EVENT_SERR    0xb
     63#define ERR_EVENT_NOMSI   0x10
     64#define ERR_EVENT_INVALBV 0x11
     65#define ERR_EVENT_AIBV    0x12
     66#define ERR_EVENT_AIRERR  0x13
     67#define ERR_EVENT_FMBA    0x2a
     68#define ERR_EVENT_FMBUP   0x2b
     69#define ERR_EVENT_FMBPRO  0x2c
     70#define ERR_EVENT_CCONF   0x30
     71#define ERR_EVENT_SERVAC  0x3a
     72#define ERR_EVENT_PERMERR 0x3b
     73
     74#define ERR_EVENT_Q_BIT 0x2
     75#define ERR_EVENT_MVN_OFFSET 16
     76
     77#define ZPCI_MSI_VEC_BITS 11
     78#define ZPCI_MSI_VEC_MASK 0x7ff
     79
     80#define ZPCI_MSI_ADDR  0xfe00000000000000ULL
     81#define ZPCI_SDMA_ADDR 0x100000000ULL
     82#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
     83
     84#define PAGE_DEFAULT_ACC        0
     85#define PAGE_DEFAULT_KEY        (PAGE_DEFAULT_ACC << 4)
     86
     87/* I/O Translation Anchor (IOTA) */
     88enum ZpciIoatDtype {
     89    ZPCI_IOTA_STO = 0,
     90    ZPCI_IOTA_RTTO = 1,
     91    ZPCI_IOTA_RSTO = 2,
     92    ZPCI_IOTA_RFTO = 3,
     93    ZPCI_IOTA_PFAA = 4,
     94    ZPCI_IOTA_IOPFAA = 5,
     95    ZPCI_IOTA_IOPTO = 7
     96};
     97
     98#define ZPCI_IOTA_IOT_ENABLED           0x800ULL
     99#define ZPCI_IOTA_DT_ST                 (ZPCI_IOTA_STO  << 2)
    100#define ZPCI_IOTA_DT_RT                 (ZPCI_IOTA_RTTO << 2)
    101#define ZPCI_IOTA_DT_RS                 (ZPCI_IOTA_RSTO << 2)
    102#define ZPCI_IOTA_DT_RF                 (ZPCI_IOTA_RFTO << 2)
    103#define ZPCI_IOTA_DT_PF                 (ZPCI_IOTA_PFAA << 2)
    104#define ZPCI_IOTA_FS_4K                 0
    105#define ZPCI_IOTA_FS_1M                 1
    106#define ZPCI_IOTA_FS_2G                 2
    107#define ZPCI_KEY                        (PAGE_DEFAULT_KEY << 5)
    108
    109#define ZPCI_IOTA_STO_FLAG  (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
    110#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
    111#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
    112#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
    113#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
    114                             ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
    115
    116/* I/O Region and segment tables */
    117#define ZPCI_INDEX_MASK         0x7ffULL
    118
    119#define ZPCI_TABLE_TYPE_MASK    0xc
    120#define ZPCI_TABLE_TYPE_RFX     0xc
    121#define ZPCI_TABLE_TYPE_RSX     0x8
    122#define ZPCI_TABLE_TYPE_RTX     0x4
    123#define ZPCI_TABLE_TYPE_SX      0x0
    124
    125#define ZPCI_TABLE_LEN_RFX      0x3
    126#define ZPCI_TABLE_LEN_RSX      0x3
    127#define ZPCI_TABLE_LEN_RTX      0x3
    128
    129#define ZPCI_TABLE_OFFSET_MASK  0xc0
    130#define ZPCI_TABLE_SIZE         0x4000
    131#define ZPCI_TABLE_ALIGN        ZPCI_TABLE_SIZE
    132#define ZPCI_TABLE_ENTRY_SIZE   (sizeof(unsigned long))
    133#define ZPCI_TABLE_ENTRIES      (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
    134
    135#define ZPCI_TABLE_BITS         11
    136#define ZPCI_PT_BITS            8
    137#define ZPCI_ST_SHIFT           (ZPCI_PT_BITS + TARGET_PAGE_BITS)
    138#define ZPCI_RT_SHIFT           (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
    139
    140#define ZPCI_RTE_FLAG_MASK      0x3fffULL
    141#define ZPCI_RTE_ADDR_MASK      (~ZPCI_RTE_FLAG_MASK)
    142#define ZPCI_STE_FLAG_MASK      0x7ffULL
    143#define ZPCI_STE_ADDR_MASK      (~ZPCI_STE_FLAG_MASK)
    144
    145#define ZPCI_SFAA_MASK          (~((1ULL << 20) - 1))
    146
    147/* I/O Page tables */
    148#define ZPCI_PTE_VALID_MASK             0x400
    149#define ZPCI_PTE_INVALID                0x400
    150#define ZPCI_PTE_VALID                  0x000
    151#define ZPCI_PT_SIZE                    0x800
    152#define ZPCI_PT_ALIGN                   ZPCI_PT_SIZE
    153#define ZPCI_PT_ENTRIES                 (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
    154#define ZPCI_PT_MASK                    (ZPCI_PT_ENTRIES - 1)
    155
    156#define ZPCI_PTE_FLAG_MASK              0xfffULL
    157#define ZPCI_PTE_ADDR_MASK              (~ZPCI_PTE_FLAG_MASK)
    158
    159/* Shared bits */
    160#define ZPCI_TABLE_VALID                0x00
    161#define ZPCI_TABLE_INVALID              0x20
    162#define ZPCI_TABLE_PROTECTED            0x200
    163#define ZPCI_TABLE_UNPROTECTED          0x000
    164#define ZPCI_TABLE_FC                   0x400
    165
    166#define ZPCI_TABLE_VALID_MASK           0x20
    167#define ZPCI_TABLE_PROT_MASK            0x200
    168
    169#define ZPCI_ETT_RT 1
    170#define ZPCI_ETT_ST 0
    171#define ZPCI_ETT_PT -1
    172
    173/* PCI Function States
    174 *
    175 * reserved: default; device has just been plugged or is in progress of being
    176 *           unplugged
    177 * standby: device is present but not configured; transition from any
    178 *          configured state/to this state via sclp configure/deconfigure
    179 *
    180 * The following states make up the "configured" meta-state:
    181 * disabled: device is configured but not enabled; transition between this
    182 *           state and enabled via clp enable/disable
    183 * enbaled: device is ready for use; transition to disabled via clp disable;
    184 *          may enter an error state
    185 * blocked: ignore all DMA and interrupts; transition back to enabled or from
    186 *          error state via mpcifc
    187 * error: an error occurred; transition back to enabled via mpcifc
    188 * permanent error: an unrecoverable error occurred; transition to standby via
    189 *                  sclp deconfigure
    190 */
    191typedef enum {
    192    ZPCI_FS_RESERVED,
    193    ZPCI_FS_STANDBY,
    194    ZPCI_FS_DISABLED,
    195    ZPCI_FS_ENABLED,
    196    ZPCI_FS_BLOCKED,
    197    ZPCI_FS_ERROR,
    198    ZPCI_FS_PERMANENT_ERROR,
    199} ZpciState;
    200
    201typedef struct SeiContainer {
    202    QTAILQ_ENTRY(SeiContainer) link;
    203    uint32_t fid;
    204    uint32_t fh;
    205    uint8_t cc;
    206    uint16_t pec;
    207    uint64_t faddr;
    208    uint32_t e;
    209} SeiContainer;
    210
    211typedef struct PciCcdfErr {
    212    uint32_t reserved1;
    213    uint32_t fh;
    214    uint32_t fid;
    215    uint32_t e;
    216    uint64_t faddr;
    217    uint32_t reserved3;
    218    uint16_t reserved4;
    219    uint16_t pec;
    220} QEMU_PACKED PciCcdfErr;
    221
    222typedef struct PciCcdfAvail {
    223    uint32_t reserved1;
    224    uint32_t fh;
    225    uint32_t fid;
    226    uint32_t reserved2;
    227    uint32_t reserved3;
    228    uint32_t reserved4;
    229    uint32_t reserved5;
    230    uint16_t reserved6;
    231    uint16_t pec;
    232} QEMU_PACKED PciCcdfAvail;
    233
    234typedef struct ChscSeiNt2Res {
    235    uint16_t length;
    236    uint16_t code;
    237    uint16_t reserved1;
    238    uint8_t reserved2;
    239    uint8_t nt;
    240    uint8_t flags;
    241    uint8_t reserved3;
    242    uint8_t reserved4;
    243    uint8_t cc;
    244    uint32_t reserved5[13];
    245    uint8_t ccdf[4016];
    246} QEMU_PACKED ChscSeiNt2Res;
    247
    248typedef struct S390MsixInfo {
    249    uint8_t table_bar;
    250    uint8_t pba_bar;
    251    uint16_t entries;
    252    uint32_t table_offset;
    253    uint32_t pba_offset;
    254} S390MsixInfo;
    255
    256typedef struct S390IOTLBEntry {
    257    uint64_t iova;
    258    uint64_t translated_addr;
    259    uint64_t len;
    260    uint64_t perm;
    261} S390IOTLBEntry;
    262
    263typedef struct S390PCIDMACount {
    264    int id;
    265    int users;
    266    uint32_t avail;
    267    QTAILQ_ENTRY(S390PCIDMACount) link;
    268} S390PCIDMACount;
    269
    270struct S390PCIIOMMU {
    271    Object parent_obj;
    272    S390PCIBusDevice *pbdev;
    273    AddressSpace as;
    274    MemoryRegion mr;
    275    IOMMUMemoryRegion iommu_mr;
    276    bool enabled;
    277    uint64_t g_iota;
    278    uint64_t pba;
    279    uint64_t pal;
    280    GHashTable *iotlb;
    281    S390PCIDMACount *dma_limit;
    282};
    283
    284typedef struct S390PCIIOMMUTable {
    285    uint64_t key;
    286    S390PCIIOMMU *iommu[PCI_SLOT_MAX];
    287} S390PCIIOMMUTable;
    288
    289/* Function Measurement Block */
    290#define DEFAULT_MUI 4000
    291#define UPDATE_U_BIT 0x1ULL
    292#define FMBK_MASK 0xfULL
    293
    294typedef struct ZpciFmbFmt0 {
    295    uint64_t dma_rbytes;
    296    uint64_t dma_wbytes;
    297} ZpciFmbFmt0;
    298
    299#define ZPCI_FMB_CNT_LD    0
    300#define ZPCI_FMB_CNT_ST    1
    301#define ZPCI_FMB_CNT_STB   2
    302#define ZPCI_FMB_CNT_RPCIT 3
    303#define ZPCI_FMB_CNT_MAX   4
    304
    305#define ZPCI_FMB_FORMAT    0
    306
    307typedef struct ZpciFmb {
    308    uint32_t format;
    309    uint32_t sample;
    310    uint64_t last_update;
    311    uint64_t counter[ZPCI_FMB_CNT_MAX];
    312    ZpciFmbFmt0 fmt0;
    313} ZpciFmb;
    314QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb");
    315
    316#define ZPCI_DEFAULT_FN_GRP 0x20
    317typedef struct S390PCIGroup {
    318    ClpRspQueryPciGrp zpci_group;
    319    int id;
    320    QTAILQ_ENTRY(S390PCIGroup) link;
    321} S390PCIGroup;
    322S390PCIGroup *s390_group_create(int id);
    323S390PCIGroup *s390_group_find(int id);
    324
    325struct S390PCIBusDevice {
    326    DeviceState qdev;
    327    PCIDevice *pdev;
    328    ZpciState state;
    329    char *target;
    330    uint16_t uid;
    331    uint32_t idx;
    332    uint32_t fh;
    333    uint32_t fid;
    334    bool fid_defined;
    335    uint64_t fmb_addr;
    336    ZpciFmb fmb;
    337    QEMUTimer *fmb_timer;
    338    uint8_t isc;
    339    uint16_t noi;
    340    uint16_t maxstbl;
    341    uint8_t sum;
    342    S390PCIGroup *pci_group;
    343    ClpRspQueryPci zpci_fn;
    344    S390MsixInfo msix;
    345    AdapterRoutes routes;
    346    S390PCIIOMMU *iommu;
    347    MemoryRegion msix_notify_mr;
    348    IndAddr *summary_ind;
    349    IndAddr *indicator;
    350    bool pci_unplug_request_processed;
    351    bool unplug_requested;
    352    QTAILQ_ENTRY(S390PCIBusDevice) link;
    353};
    354
    355struct S390PCIBus {
    356    BusState qbus;
    357};
    358
    359struct S390pciState {
    360    PCIHostState parent_obj;
    361    uint32_t next_idx;
    362    int bus_no;
    363    S390PCIBus *bus;
    364    GHashTable *iommu_table;
    365    GHashTable *zpci_table;
    366    QTAILQ_HEAD(, SeiContainer) pending_sei;
    367    QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
    368    QTAILQ_HEAD(, S390PCIDMACount) zpci_dma_limit;
    369    QTAILQ_HEAD(, S390PCIGroup) zpci_groups;
    370};
    371
    372S390pciState *s390_get_phb(void);
    373int pci_chsc_sei_nt2_get_event(void *res);
    374int pci_chsc_sei_nt2_have_event(void);
    375void s390_pci_sclp_configure(SCCB *sccb);
    376void s390_pci_sclp_deconfigure(SCCB *sccb);
    377void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
    378void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
    379void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
    380                                   uint64_t faddr, uint32_t e);
    381uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr,
    382                                  S390IOTLBEntry *entry);
    383S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx);
    384S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh);
    385S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid);
    386S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s,
    387                                              const char *target);
    388S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
    389                                               S390PCIBusDevice *pbdev);
    390
    391#endif