esp.h (3636B)
1#ifndef QEMU_HW_ESP_H 2#define QEMU_HW_ESP_H 3 4#include "hw/scsi/scsi.h" 5#include "hw/sysbus.h" 6#include "qemu/fifo8.h" 7#include "qom/object.h" 8 9/* esp.c */ 10#define ESP_MAX_DEVS 7 11typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len); 12 13#define ESP_REGS 16 14#define ESP_FIFO_SZ 16 15#define ESP_CMDFIFO_SZ 32 16 17typedef struct ESPState ESPState; 18 19#define TYPE_ESP "esp" 20OBJECT_DECLARE_SIMPLE_TYPE(ESPState, ESP) 21 22struct ESPState { 23 DeviceState parent_obj; 24 25 uint8_t rregs[ESP_REGS]; 26 uint8_t wregs[ESP_REGS]; 27 qemu_irq irq; 28 qemu_irq irq_data; 29 uint8_t chip_id; 30 bool tchi_written; 31 int32_t ti_size; 32 uint32_t status; 33 uint32_t dma; 34 Fifo8 fifo; 35 SCSIBus bus; 36 SCSIDevice *current_dev; 37 SCSIRequest *current_req; 38 Fifo8 cmdfifo; 39 uint8_t cmdfifo_cdb_offset; 40 uint8_t lun; 41 uint32_t do_cmd; 42 43 bool data_in_ready; 44 uint8_t ti_cmd; 45 int dma_enabled; 46 47 uint32_t async_len; 48 uint8_t *async_buf; 49 50 ESPDMAMemoryReadWriteFunc dma_memory_read; 51 ESPDMAMemoryReadWriteFunc dma_memory_write; 52 void *dma_opaque; 53 void (*dma_cb)(ESPState *s); 54 void (*pdma_cb)(ESPState *s); 55 56 uint8_t mig_version_id; 57 58 /* Legacy fields for vmstate_esp version < 5 */ 59 uint32_t mig_dma_left; 60 uint32_t mig_deferred_status; 61 bool mig_deferred_complete; 62 uint32_t mig_ti_rptr, mig_ti_wptr; 63 uint8_t mig_ti_buf[ESP_FIFO_SZ]; 64 uint8_t mig_cmdbuf[ESP_CMDFIFO_SZ]; 65 uint32_t mig_cmdlen; 66}; 67 68#define TYPE_SYSBUS_ESP "sysbus-esp" 69OBJECT_DECLARE_SIMPLE_TYPE(SysBusESPState, SYSBUS_ESP) 70 71struct SysBusESPState { 72 /*< private >*/ 73 SysBusDevice parent_obj; 74 /*< public >*/ 75 76 MemoryRegion iomem; 77 MemoryRegion pdma; 78 uint32_t it_shift; 79 ESPState esp; 80}; 81 82#define ESP_TCLO 0x0 83#define ESP_TCMID 0x1 84#define ESP_FIFO 0x2 85#define ESP_CMD 0x3 86#define ESP_RSTAT 0x4 87#define ESP_WBUSID 0x4 88#define ESP_RINTR 0x5 89#define ESP_WSEL 0x5 90#define ESP_RSEQ 0x6 91#define ESP_WSYNTP 0x6 92#define ESP_RFLAGS 0x7 93#define ESP_WSYNO 0x7 94#define ESP_CFG1 0x8 95#define ESP_RRES1 0x9 96#define ESP_WCCF 0x9 97#define ESP_RRES2 0xa 98#define ESP_WTEST 0xa 99#define ESP_CFG2 0xb 100#define ESP_CFG3 0xc 101#define ESP_RES3 0xd 102#define ESP_TCHI 0xe 103#define ESP_RES4 0xf 104 105#define CMD_DMA 0x80 106#define CMD_CMD 0x7f 107 108#define CMD_NOP 0x00 109#define CMD_FLUSH 0x01 110#define CMD_RESET 0x02 111#define CMD_BUSRESET 0x03 112#define CMD_TI 0x10 113#define CMD_ICCS 0x11 114#define CMD_MSGACC 0x12 115#define CMD_PAD 0x18 116#define CMD_SATN 0x1a 117#define CMD_RSTATN 0x1b 118#define CMD_SEL 0x41 119#define CMD_SELATN 0x42 120#define CMD_SELATNS 0x43 121#define CMD_ENSEL 0x44 122#define CMD_DISSEL 0x45 123 124#define STAT_DO 0x00 125#define STAT_DI 0x01 126#define STAT_CD 0x02 127#define STAT_ST 0x03 128#define STAT_MO 0x06 129#define STAT_MI 0x07 130#define STAT_PIO_MASK 0x06 131 132#define STAT_TC 0x10 133#define STAT_PE 0x20 134#define STAT_GE 0x40 135#define STAT_INT 0x80 136 137#define BUSID_DID 0x07 138 139#define INTR_FC 0x08 140#define INTR_BS 0x10 141#define INTR_DC 0x20 142#define INTR_RST 0x80 143 144#define SEQ_0 0x0 145#define SEQ_MO 0x1 146#define SEQ_CD 0x4 147 148#define CFG1_RESREPT 0x40 149 150#define TCHI_FAS100A 0x4 151#define TCHI_AM53C974 0x12 152 153void esp_dma_enable(ESPState *s, int irq, int level); 154void esp_request_cancelled(SCSIRequest *req); 155void esp_command_complete(SCSIRequest *req, size_t resid); 156void esp_transfer_data(SCSIRequest *req, uint32_t len); 157void esp_hard_reset(ESPState *s); 158uint64_t esp_reg_read(ESPState *s, uint32_t saddr); 159void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val); 160extern const VMStateDescription vmstate_esp; 161int esp_pre_save(void *opaque); 162 163#endif