cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

imx_spi.h (2616B)

      1/*
      2 * IMX SPI Controller
      3 *
      4 * Copyright 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
      5 *
      6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
      7 * See the COPYING file in the top-level directory.
      8 */
      9
     10#ifndef IMX_SPI_H
     11#define IMX_SPI_H
     12
     13#include "hw/sysbus.h"
     14#include "hw/ssi/ssi.h"
     15#include "qemu/bitops.h"
     16#include "qemu/fifo32.h"
     17#include "qom/object.h"
     18
     19#define ECSPI_FIFO_SIZE 64
     20
     21#define ECSPI_RXDATA 0
     22#define ECSPI_TXDATA 1
     23#define ECSPI_CONREG 2
     24#define ECSPI_CONFIGREG 3
     25#define ECSPI_INTREG 4
     26#define ECSPI_DMAREG 5
     27#define ECSPI_STATREG 6
     28#define ECSPI_PERIODREG 7
     29#define ECSPI_TESTREG 8
     30#define ECSPI_MSGDATA 16
     31#define ECSPI_MAX 17
     32
     33/* ECSPI_CONREG */
     34#define ECSPI_CONREG_EN (1 << 0)
     35#define ECSPI_CONREG_HT (1 << 1)
     36#define ECSPI_CONREG_XCH (1 << 2)
     37#define ECSPI_CONREG_SMC (1 << 3)
     38#define ECSPI_CONREG_CHANNEL_MODE_SHIFT 4
     39#define ECSPI_CONREG_CHANNEL_MODE_LENGTH 4
     40#define ECSPI_CONREG_DRCTL_SHIFT 16
     41#define ECSPI_CONREG_DRCTL_LENGTH 2
     42#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT 18
     43#define ECSPI_CONREG_CHANNEL_SELECT_LENGTH 2
     44#define ECSPI_CONREG_BURST_LENGTH_SHIFT 20
     45#define ECSPI_CONREG_BURST_LENGTH_LENGTH 12
     46
     47/* ECSPI_CONFIGREG */
     48#define ECSPI_CONFIGREG_SS_CTL_SHIFT 8
     49#define ECSPI_CONFIGREG_SS_CTL_LENGTH 4
     50
     51/* ECSPI_INTREG */
     52#define ECSPI_INTREG_TEEN (1 << 0)
     53#define ECSPI_INTREG_TDREN (1 << 1)
     54#define ECSPI_INTREG_TFEN (1 << 2)
     55#define ECSPI_INTREG_RREN (1 << 3)
     56#define ECSPI_INTREG_RDREN (1 << 4)
     57#define ECSPI_INTREG_RFEN (1 << 5)
     58#define ECSPI_INTREG_ROEN (1 << 6)
     59#define ECSPI_INTREG_TCEN (1 << 7)
     60
     61/* ECSPI_DMAREG */
     62#define ECSPI_DMAREG_RXTDEN (1 << 31)
     63#define ECSPI_DMAREG_RXDEN (1 << 23)
     64#define ECSPI_DMAREG_TEDEN (1 << 7)
     65#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT 16
     66#define ECSPI_DMAREG_RX_THRESHOLD_LENGTH 6
     67
     68/* ECSPI_STATREG */
     69#define ECSPI_STATREG_TE (1 << 0)
     70#define ECSPI_STATREG_TDR (1 << 1)
     71#define ECSPI_STATREG_TF (1 << 2)
     72#define ECSPI_STATREG_RR (1 << 3)
     73#define ECSPI_STATREG_RDR (1 << 4)
     74#define ECSPI_STATREG_RF (1 << 5)
     75#define ECSPI_STATREG_RO (1 << 6)
     76#define ECSPI_STATREG_TC (1 << 7)
     77
     78#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
     79
     80/* number of chip selects supported */
     81#define ECSPI_NUM_CS 4
     82
     83#define TYPE_IMX_SPI "imx.spi"
     84OBJECT_DECLARE_SIMPLE_TYPE(IMXSPIState, IMX_SPI)
     85
     86struct IMXSPIState {
     87    /* <private> */
     88    SysBusDevice parent_obj;
     89
     90    /* <public> */
     91    MemoryRegion iomem;
     92
     93    qemu_irq irq;
     94
     95    qemu_irq cs_lines[ECSPI_NUM_CS];
     96
     97    SSIBus *bus;
     98
     99    uint32_t regs[ECSPI_MAX];
    100
    101    Fifo32 rx_fifo;
    102    Fifo32 tx_fifo;
    103
    104    int16_t burst_length;
    105};
    106
    107#endif /* IMX_SPI_H */