cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

pl022.h (1208B)

      1/*
      2 * ARM PrimeCell PL022 Synchronous Serial Port
      3 *
      4 * Copyright (c) 2007 CodeSourcery.
      5 * Written by Paul Brook
      6 *
      7 * This program is free software; you can redistribute it and/or modify
      8 * it under the terms of the GNU General Public License version 2 or
      9 * (at your option) any later version.
     10 */
     11
     12/*
     13 * This is a model of the Arm PrimeCell PL022 synchronous serial port.
     14 * The PL022 TRM is:
     15 * https://developer.arm.com/documentation/ddi0194/latest
     16 *
     17 * QEMU interface:
     18 * + sysbus IRQ: SSPINTR combined interrupt line
     19 * + sysbus MMIO region 0: MemoryRegion for the device's registers
     20 */
     21
     22#ifndef HW_SSI_PL022_H
     23#define HW_SSI_PL022_H
     24
     25#include "hw/sysbus.h"
     26#include "qom/object.h"
     27
     28#define TYPE_PL022 "pl022"
     29OBJECT_DECLARE_SIMPLE_TYPE(PL022State, PL022)
     30
     31struct PL022State {
     32    SysBusDevice parent_obj;
     33
     34    MemoryRegion iomem;
     35    uint32_t cr0;
     36    uint32_t cr1;
     37    uint32_t bitmask;
     38    uint32_t sr;
     39    uint32_t cpsr;
     40    uint32_t is;
     41    uint32_t im;
     42    /* The FIFO head points to the next empty entry.  */
     43    int tx_fifo_head;
     44    int rx_fifo_head;
     45    int tx_fifo_len;
     46    int rx_fifo_len;
     47    uint16_t tx_fifo[8];
     48    uint16_t rx_fifo[8];
     49    qemu_irq irq;
     50    SSIBus *ssi;
     51};
     52
     53#endif