cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt

npcm7xx_timer.h (3550B)

      1/*
      2 * Nuvoton NPCM7xx Timer Controller
      3 *
      4 * Copyright 2020 Google LLC
      5 *
      6 * This program is free software; you can redistribute it and/or modify it
      7 * under the terms of the GNU General Public License as published by the
      8 * Free Software Foundation; either version 2 of the License, or
      9 * (at your option) any later version.
     10 *
     11 * This program is distributed in the hope that it will be useful, but WITHOUT
     12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
     14 * for more details.
     15 */
     16#ifndef NPCM7XX_TIMER_H
     17#define NPCM7XX_TIMER_H
     18
     19#include "exec/memory.h"
     20#include "hw/sysbus.h"
     21#include "qemu/timer.h"
     22
     23/* Each Timer Module (TIM) instance holds five 25 MHz timers. */
     24#define NPCM7XX_TIMERS_PER_CTRL (5)
     25
     26/*
     27 * Number of registers in our device state structure. Don't change this without
     28 * incrementing the version_id in the vmstate.
     29 */
     30#define NPCM7XX_TIMER_NR_REGS (0x54 / sizeof(uint32_t))
     31
     32/* The basic watchdog timer period is 2^14 clock cycles. */
     33#define NPCM7XX_WATCHDOG_BASETIME_SHIFT 14
     34
     35#define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
     36
     37typedef struct NPCM7xxTimerCtrlState NPCM7xxTimerCtrlState;
     38
     39/**
     40 * struct NPCM7xxBaseTimer - Basic functionality that both regular timer and
     41 * watchdog timer use.
     42 * @qtimer: QEMU timer that notifies us on expiration.
     43 * @expires_ns: Absolute virtual expiration time.
     44 * @remaining_ns: Remaining time until expiration if timer is paused.
     45 */
     46typedef struct NPCM7xxBaseTimer {
     47    QEMUTimer   qtimer;
     48    int64_t     expires_ns;
     49    int64_t     remaining_ns;
     50} NPCM7xxBaseTimer;
     51
     52/**
     53 * struct NPCM7xxTimer - Individual timer state.
     54 * @ctrl: The timer module that owns this timer.
     55 * @irq: GIC interrupt line to fire on expiration (if enabled).
     56 * @base_timer: The basic timer functionality for this timer.
     57 * @tcsr: The Timer Control and Status Register.
     58 * @ticr: The Timer Initial Count Register.
     59 */
     60typedef struct NPCM7xxTimer {
     61    NPCM7xxTimerCtrlState *ctrl;
     62
     63    qemu_irq    irq;
     64    NPCM7xxBaseTimer base_timer;
     65
     66    uint32_t    tcsr;
     67    uint32_t    ticr;
     68} NPCM7xxTimer;
     69
     70/**
     71 * struct NPCM7xxWatchdogTimer - The watchdog timer state.
     72 * @ctrl: The timer module that owns this timer.
     73 * @irq: GIC interrupt line to fire on expiration (if enabled).
     74 * @reset_signal: The GPIO used to send a reset signal.
     75 * @base_timer: The basic timer functionality for this timer.
     76 * @wtcr: The Watchdog Timer Control Register.
     77 */
     78typedef struct NPCM7xxWatchdogTimer {
     79    NPCM7xxTimerCtrlState *ctrl;
     80
     81    qemu_irq            irq;
     82    qemu_irq            reset_signal;
     83    NPCM7xxBaseTimer base_timer;
     84
     85    uint32_t            wtcr;
     86} NPCM7xxWatchdogTimer;
     87
     88/**
     89 * struct NPCM7xxTimerCtrlState - Timer Module device state.
     90 * @parent: System bus device.
     91 * @iomem: Memory region through which registers are accessed.
     92 * @index: The index of this timer module.
     93 * @tisr: The Timer Interrupt Status Register.
     94 * @timer: The five individual timers managed by this module.
     95 * @watchdog_timer: The watchdog timer managed by this module.
     96 */
     97struct NPCM7xxTimerCtrlState {
     98    SysBusDevice parent;
     99
    100    MemoryRegion iomem;
    101
    102    uint32_t    tisr;
    103
    104    Clock       *clock;
    105    NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
    106    NPCM7xxWatchdogTimer watchdog_timer;
    107};
    108
    109#define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
    110#define NPCM7XX_TIMER(obj)                                              \
    111    OBJECT_CHECK(NPCM7xxTimerCtrlState, (obj), TYPE_NPCM7XX_TIMER)
    112
    113#endif /* NPCM7XX_TIMER_H */